Ross Thompson
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a130a96b45
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Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
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2022-12-04 01:20:51 -06:00 |
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Ross Thompson
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3dea04e644
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Moved selectedway mux into cacheway. It makes way more sense there.
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2022-12-04 01:15:47 -06:00 |
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Ross Thompson
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f557150cae
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Rename LineByteMux to FetchbufferbyteSel.
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2022-12-04 01:00:04 -06:00 |
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Ross Thompson
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fc05e27416
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Updated riscv arch test removed misaligned1.
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2022-12-04 00:18:10 +00:00 |
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Ross Thompson
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350fdd944d
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Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit fb221d7b64.
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2022-12-04 00:01:58 +00:00 |
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Ross Thompson
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87ce09f7d9
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Removed old flow directory.
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2022-12-03 10:28:39 -06:00 |
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Ross Thompson
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45bc732b4d
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removed imperas-riscv-tests-deleteme
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2022-12-03 00:18:42 +00:00 |
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Ross Thompson
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d8fdc179f1
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removed unusedsrc directory as it was large 384MB!
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2022-12-02 17:37:06 -06:00 |
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Ross Thompson
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ae4c36936d
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Removed design ware mult.
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2022-12-02 16:51:12 -06:00 |
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cturek
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fb221d7b64
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Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
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2022-12-02 21:44:29 +00:00 |
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cturek
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04ac350a29
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Added flops to preproc
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2022-12-02 20:31:08 +00:00 |
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David Harris
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3a07d56d33
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Renamed FPUStallD to FCvtIntStallD
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2022-12-02 11:55:23 -08:00 |
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David Harris
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1b0f878c16
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Renamed DivStartE to IFDivStartE
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2022-12-02 11:30:49 -08:00 |
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David Harris
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db5f3c15a4
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FPU divider working with execute stage stall
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2022-12-02 11:11:53 -08:00 |
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David Harris
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a86c9de36b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-02 04:28:50 -08:00 |
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David Harris
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6079a01bc8
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update test list
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2022-12-02 04:28:47 -08:00 |
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Ross Thompson
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602d191580
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 22:36:07 -06:00 |
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David Harris
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7c3e8553d1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 16:27:36 -08:00 |
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David Harris
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0d23ab3ec1
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reorder tests
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2022-12-01 16:27:33 -08:00 |
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Ross Thompson
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3442b04f9e
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Properly flush cacheLRU.
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2022-12-01 17:32:58 -06:00 |
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David Harris
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3a8602523e
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FPU test list
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2022-12-01 10:18:36 -08:00 |
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Ross Thompson
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e403800ce8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 11:47:54 -06:00 |
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Ross Thompson
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5025664cb0
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Removed unused port on cacheway.
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2022-12-01 11:47:48 -06:00 |
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David Harris
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28996d0b12
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 08:15:51 -08:00 |
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David Harris
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1bd639be6d
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code cleanup
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2022-12-01 08:15:48 -08:00 |
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Ross Thompson
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e6bd86f4fa
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 17:19:04 -06:00 |
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David Harris
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4ddc8fd603
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signal sufixes in integer division
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2022-11-30 15:15:37 -08:00 |
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Ross Thompson
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fa22484cfe
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Reverted the IROM/DTIM address range modelsim assignment.
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2022-11-30 17:13:33 -06:00 |
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Ross Thompson
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2f582cd91f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 13:30:37 -06:00 |
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Ross Thompson
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a6355b1dcb
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More optimization.
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2022-11-30 11:26:48 -06:00 |
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Ross Thompson
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0aa7ce0b24
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Removed reset on dirty cache bits.
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2022-11-30 11:04:37 -06:00 |
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Ross Thompson
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cedb234013
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Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
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2022-11-30 11:01:25 -06:00 |
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Ross Thompson
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0454eb95ad
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Preparing to merge dirty and tag srams.
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2022-11-30 10:40:48 -06:00 |
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Ross Thompson
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de538d1c2f
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Intermediate commit. Replaced flip flop dirty bit array with sram.
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2022-11-30 00:08:31 -06:00 |
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cturek
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10c2d45888
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div tests in sim-wally
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2022-11-30 02:32:04 +00:00 |
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Ross Thompson
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453ea36512
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Optimization of cacheway.
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2022-11-29 18:30:47 -06:00 |
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Ross Thompson
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fbf543bf57
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Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
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2022-11-29 17:19:31 -06:00 |
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Ross Thompson
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0277227323
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 14:57:38 -06:00 |
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Ross Thompson
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b5718c9baa
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Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
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2022-11-29 14:51:09 -06:00 |
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Ross Thompson
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96cc4c7ebe
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Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
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2022-11-29 14:09:48 -06:00 |
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Kip Macsai-Goren
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c7c578c104
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 10:43:44 -08:00 |
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Kip Macsai-Goren
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44ea8d8b22
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added failing satp invalid tests to regression
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2022-11-29 10:43:38 -08:00 |
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Ross Thompson
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da82ab3712
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 11:52:35 -06:00 |
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Ross Thompson
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78acd40424
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Renamed signals in the cache.
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2022-11-29 10:52:40 -06:00 |
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Kip Macsai-Goren
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9b1765ce92
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added tests for invalid address being written to satp. Not passing regression
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2022-11-27 13:22:35 -08:00 |
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Ross Thompson
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6dd5668d21
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-22 18:07:32 -06:00 |
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cturek
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bdb9e24a66
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Almost done with Int division
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2022-11-22 22:22:59 +00:00 |
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cturek
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78c2ce5649
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Updated testbench/wave for fdivsqrt new start signals
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2022-11-22 22:22:26 +00:00 |
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Ross Thompson
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279f5bc615
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Cleanup cacheLRU.
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2022-11-22 14:59:01 -06:00 |
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Ross Thompson
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e1dbe58632
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File name change for cachereplacement policy to cacheLRU
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2022-11-20 22:35:02 -06:00 |
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