Ross Thompson
9f7e3f147b
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
David Harris
d356a0d29f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-13 21:46:00 +00:00
David Harris
e3f6c398b5
Mixed C and assembly language test cases; SRT initial version passing tests
2022-01-13 21:45:54 +00:00
Ross Thompson
0b06fa12ef
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
93cb24476f
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
Ross Thompson
4bcabd1a55
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
654a33bf92
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
861450c4d6
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
000d713cb5
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
26fb09c868
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
6b483e621d
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
48c036a923
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-12 14:17:16 -06:00
Ross Thompson
796316495d
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
ecd3912900
Set rv32ic to not use icache.
2022-01-12 14:10:09 -06:00
Ross Thompson
2ed052f152
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-12 13:29:19 -06:00
Ross Thompson
87485f9f64
Improve wavefile by adding performance counters.
2022-01-12 10:53:29 -06:00
Kip Macsai-Goren
c99456d5e7
Fixed PMA regions, Added passing PMA tests to regression
2022-01-10 22:08:26 +00:00
David Harris
4cae11ad28
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
50c17f2a03
Removed unused coremark_bare
2022-01-10 05:05:55 +00:00
David Harris
467aac8463
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
55456e465c
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
e01c8bc5f6
Added performance counters to wavefile.
2022-01-09 22:42:14 -06:00
Ross Thompson
3109fa1383
Fixed wavefile.
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Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
David Harris
89ee6c778e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-09 14:39:33 +00:00
Ross Thompson
b6ae6fea27
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
573ff47763
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
453a794f86
Testbench directory cleanup
2022-01-07 17:02:16 +00:00
David Harris
3d2671a8b0
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
913a78323c
moved proposed-sdc
2022-01-07 12:44:21 +00:00
David Harris
6c0cd5ef20
piplined directory cleanup
2022-01-07 12:43:50 +00:00
David Harris
8481c93e1b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
Ross Thompson
de3bbd3fe0
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
...
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
David Harris
261882bf78
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
fa0080ca70
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
...
assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
2df92af488
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
27c1d73cb1
Code cleanup
2022-01-07 04:07:04 +00:00
Ross Thompson
5402b55c44
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 17:19:20 -06:00
Ross Thompson
0438975e27
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
David Harris
0c8d556311
Tests cleanup:
2022-01-06 23:07:22 +00:00
David Harris
6fafabbfad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
53637049b7
Makefile make allclean
2022-01-06 23:04:30 +00:00
David Harris
ae64b859c3
Fixed multiplier nan boxing bug
2022-01-06 23:03:29 +00:00
Katherine Parry
631d05dcdc
some FPU test fixes
2022-01-06 23:03:20 +00:00
Ross Thompson
e0740034f0
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
David Harris
3bfe23bc75
More FP unpacking fix
2022-01-06 22:22:22 +00:00
David Harris
770780e394
Floating point test cleanup
2022-01-06 21:45:16 +00:00
David Harris
a5a89e58a8
Fixed unpacking bug; regression runs again
2022-01-06 18:22:30 +00:00
David Harris
eff9cec415
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 18:10:32 +00:00
David Harris
aca26de498
FPU debug and configurable logic cleanup
2022-01-06 18:10:25 +00:00
