Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
4,528 Commits 5 Branches 2 Tags 53 MiB
9dd0d66ab5
Commit Graph

101 Commits

Author SHA1 Message Date
Ross Thompson
a12016e69b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
bdfca503fa Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
d5f524a15e Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
Ross Thompson
60e6c1ffa7 Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
David Harris
48705457d5 LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
Ross Thompson
fcbb577f31 Cache mods to be consistant with diagrams. 2022-02-14 12:40:51 -06:00
Ross Thompson
6e1a0af5d0 Eliminated more ports in cacheway. 2022-02-13 15:53:46 -06:00
Ross Thompson
a440bc2ac5 More cache cleanup. 2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd Changed names of signals in cache. 2022-02-13 15:06:18 -06:00
Ross Thompson
f87a6f2c63 More cache cleanup. 2022-02-13 12:38:39 -06:00
Ross Thompson
f5c4bca47e Formating improvements to cache. 2022-02-11 23:10:58 -06:00
Ross Thompson
ae2011eb07 Reduced seladr to 1 bit as second bit is same as selflush. 2022-02-11 22:41:36 -06:00
Ross Thompson
cb3d71a63d Reduced complexity of the address selection during flush. 2022-02-11 22:27:27 -06:00
Ross Thompson
a0ee2f3d99 Removed redundant signals from cache. 2022-02-11 22:23:47 -06:00
Ross Thompson
411997010b Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
3a0af5d9e9 Cleanup + critical path optimizations. 2022-02-10 11:11:16 -06:00
Ross Thompson
fc68c2f09a Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
e00d404154 More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
2a989e6d05 More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
911ee36b22 Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
498388c636 Cache cleanup write enables. 2022-02-08 17:52:09 -06:00
Ross Thompson
492c1473f3 Preparing to make a major change to the cache's write enables. 2022-02-08 09:47:01 -06:00
Ross Thompson
190d619940 cachefsm cleanup. 2022-02-07 22:09:56 -06:00
Ross Thompson
ca459a5915 Removed VDWriteEnable. 2022-02-07 21:59:18 -06:00
Ross Thompson
494802b2e1 more partial cleanup of fsm and write enables. 2022-02-07 17:41:56 -06:00
Ross Thompson
23a60d9875 Progress towards simplifying the cache's write enables. 2022-02-07 17:23:09 -06:00
Ross Thompson
308cc34d6f Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
Ross Thompson
1766c0f5ba Removed unused ports from caches and buses. 2022-02-04 22:52:51 -06:00
Ross Thompson
c846368537 Moved the sub cache line read logic to lsu/ifu. 2022-02-04 20:42:53 -06:00
Ross Thompson
f6f0539e10 Got separate module for the sub cache line read. 2022-02-04 20:23:09 -06:00
Ross Thompson
ceb2cc30b9 Second optimization of save/restore. 2022-02-04 14:35:12 -06:00
Ross Thompson
498c2b589a Optimization of cache save/restore. 2022-02-04 14:21:04 -06:00
Ross Thompson
83fdedcec6 Working first cut of the cache changes moving the replay to a save/restore. 
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
 2022-02-04 13:31:32 -06:00
David Harris
9b6a4d1d52 cacheway cleanup 2022-02-03 16:52:22 +00:00
David Harris
7a8cc5ef21 cacheway cleanup 2022-02-03 16:33:01 +00:00
David Harris
e92461159d cache cleanup 2022-02-03 15:36:11 +00:00
David Harris
b967bcede2 LSU Cleanup 2022-01-15 01:11:17 +00:00
David Harris
3d2671a8b0 Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
Ross Thompson
fa0080ca70 Modified the mmu to not mux the lower 12 bits of the physical address and instead directly 
assign from the input non translated virtual address.  Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address.  This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
 2022-01-06 23:19:09 -06:00
Ross Thompson
0438975e27 Minor optimization to cache replacement. 2022-01-06 17:19:14 -06:00
Ross Thompson
e0740034f0 Clean up of cachefsm. 2022-01-06 16:32:49 -06:00
Ross Thompson
a4afc1bc54 More name cleanup in cache. 2022-01-05 22:37:53 -06:00
Ross Thompson
e74e8c2e86 Changed names of address in caches. 
Removed old cache files.
 2022-01-05 22:19:36 -06:00
Ross Thompson
da585b30f9 Slower but correct implementation of flush. 2022-01-05 16:57:22 -06:00
Ross Thompson
7086a0ed08 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-05 14:15:27 -06:00
Ross Thompson
cc51a27a34 Fixed bug with flush dirty not cleared in the correct cache line. 2022-01-05 14:14:01 -06:00
David Harris
da5ead23bf Removed more generate statements 2022-01-05 16:01:03 +00:00
Ross Thompson
98be8201b2 Renamed most signals inside cache.sv so they are agnostic to i or d. 2022-01-04 23:52:42 -06:00
Ross Thompson
fffaf654e6 the i and d caches now share common verilog. 2022-01-04 23:40:37 -06:00