Rose Thompson
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9c1779a2d5
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Added some documenation about sparse-checkout for verilog-ethernet submodule.
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2024-07-19 13:11:48 -05:00 |
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Rose Thompson
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79d0cb96c2
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Added verilog-ethernet as a submodule. Hoping we can make use of sparse-checkout as there are so many files in this repo.
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2024-07-18 18:22:26 -05:00 |
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Ross Thompson
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c72f0fd504
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Added csr comparison.
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2024-07-11 10:49:06 -05:00 |
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Ross Thompson
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abf9da01ab
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code cleanup.
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2024-07-11 10:41:34 -05:00 |
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Ross Thompson
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f0096f5a43
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Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
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2024-07-10 15:10:37 -05:00 |
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Ross Thompson
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e6dc962d11
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Yay! the trigger is correctly working now!
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2024-07-10 12:05:10 -05:00 |
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Ross Thompson
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cf986b5fb8
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Really close to having the trigger in module work.
Can trigger on the data of the correct frame, but trigger in is still not
working.
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2024-07-09 19:04:51 -05:00 |
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Ross Thompson
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6734685333
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Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.
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2024-07-09 19:04:18 -05:00 |
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Ross Thompson
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e0a1f0e39f
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Really close now.
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2024-07-09 14:21:43 -05:00 |
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Ross Thompson
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e488ee7225
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Correctly sending the ethernet frame on a mismatch. Now just need to get vivado to actually trigger.
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2024-07-09 14:16:13 -05:00 |
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Ross Thompson
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fd170a6583
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Getting closer.
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2024-07-09 14:09:56 -05:00 |
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Ross Thompson
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bf69a2e1cd
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Updated to use the newest imperasDV.
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2024-07-09 12:30:18 -05:00 |
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Ross Thompson
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dc97ee5f82
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Have some sample code which I know works transmisting a packet.
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2024-07-02 09:12:34 -07:00 |
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Ross Thompson
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ccf4bb8ddc
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Maybe have the incircuit trigger working.
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2024-06-26 16:15:46 -07:00 |
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Ross Thompson
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612a281f62
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Added module to receive ethernet frame and trigger the ila.
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2024-06-26 11:05:31 -07:00 |
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Ross Thompson
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74189e1e4b
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Have vivado triggering the ILA after the mismatch but the latency is way too long.
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2024-06-25 17:04:14 -07:00 |
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Ross Thompson
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fa26c9a8b5
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Added pipe to vivado to create ila trigger from rvvidaemon.
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2024-06-25 13:07:46 -07:00 |
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Ross Thompson
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249d58244a
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It's working!!!!!!
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2024-06-20 15:48:30 -07:00 |
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Ross Thompson
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1c6ebb86a3
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Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
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2024-06-20 12:54:12 -07:00 |
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Ross Thompson
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2581ea0b74
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Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames.
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2024-06-18 16:48:49 -07:00 |
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Ross Thompson
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00e0549c36
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I know what is wrong now. The ethernet device IP is not correctly generating the mii nibble stream. Some nibbles are dropped in each 4-byte word.
The default input interface to the interface is 8-bit and I used 32-bit. I suspect there is a bug in the implementation for non-8-bit interfaces.
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2024-06-18 07:44:19 -07:00 |
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Ross Thompson
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93829ce509
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Success! We have some instructions comparing across the FPGA and IDV!
However I'm still losing ethernet frames.
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2024-06-17 13:41:40 -07:00 |
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Ross Thompson
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598770da51
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Getting much closer to a working version.
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2024-06-17 12:37:10 -07:00 |
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Ross Thompson
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cccb40e4b5
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Got the tracer not overrunning ethernet buffers so frames are not being dropped.
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2024-06-17 09:16:24 -07:00 |
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Ross Thompson
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82b54c0887
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Got IDV properly initalized.
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2024-06-17 09:15:59 -07:00 |
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Ross Thompson
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47523c97ac
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Getting closer to figuring out the lost ethernet frame bugs.
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2024-06-13 15:46:54 -07:00 |
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Ross Thompson
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c9f51df34a
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Fixed bug in rvvi reset.
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2024-06-12 14:47:32 -07:00 |
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Ross Thompson
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323dbd348e
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Progress.
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2024-06-12 12:54:21 -07:00 |
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Ross Thompson
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f5d4db68b1
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Modified rvvidaemon to populate a struct with all the relavent fields.
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2024-06-12 08:56:16 -07:00 |
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Ross Thompson
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3e7d07dfb6
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Better.
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2024-06-11 17:14:59 -07:00 |
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Ross Thompson
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8bce2fc739
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Getting closer.
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2024-06-11 16:21:53 -07:00 |
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Ross Thompson
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c9f3da51cb
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getting closer to full reconstruction of rvvi.
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2024-06-11 15:35:35 -07:00 |
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Ross Thompson
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3d9f796f21
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Better parsing of rvvi.
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2024-06-11 14:36:34 -07:00 |
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Ross Thompson
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563980443a
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Merge branch 'main' into rvvi
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2024-06-10 18:10:23 -07:00 |
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Ross Thompson
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49912589f5
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Added rvviApi.h to rvvidaemon.
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2024-06-10 17:57:24 -07:00 |
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Ross Thompson
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e16cf9d739
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Added Makefile to compile rvvidaemon
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2024-06-10 16:56:53 -07:00 |
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Rose Thompson
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72c1374d9c
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Minor code cleanup.
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2024-06-04 15:11:57 -05:00 |
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Rose Thompson
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f0ed780745
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progress.
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2024-06-04 15:11:03 -05:00 |
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Rose Thompson
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07d66c246c
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Update.
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2024-06-04 11:59:17 -05:00 |
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Rose Thompson
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08ff88f428
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On the way towards complete reconstruction of the RVVI trace.
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2024-06-04 11:47:46 -05:00 |
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Rose Thompson
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fc62f80407
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Closer to fully working hardware tracer.
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2024-06-04 11:31:05 -05:00 |
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Rose Thompson
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80f98b3223
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now have a working ethernet daemon to collect frames and partially decode into RVVI.
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2024-06-04 10:20:51 -05:00 |
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Rose Thompson
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dc904cdbbb
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The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field.
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2024-06-03 18:10:25 -05:00 |
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Rose Thompson
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0ca10e7ee2
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Last of the branch predictor signal name updates.
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2024-06-02 17:01:51 -05:00 |
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Rose Thompson
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04744032d8
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Updated more signal names to match book.
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2024-06-02 16:59:11 -05:00 |
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Rose Thompson
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b45b7ff7d6
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Signal name changes to match book.
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2024-06-02 16:32:25 -05:00 |
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Rose Thompson
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731e1fe08f
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Updated spill logic to reflect changes in textbook.
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2024-06-02 15:48:42 -05:00 |
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Rose Thompson
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3da62558ec
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Updated readme.
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2024-06-01 11:12:30 -05:00 |
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Rose Thompson
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2382677f8f
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Got the directory mode wsim working!
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2024-06-01 10:56:37 -05:00 |
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Rose Thompson
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224b8469ab
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Updated readme to reflect changes to wsim.
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2024-06-01 09:58:10 -05:00 |
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