185 Commits

Author	SHA1	Message	Date
Ross Thompson	f23817bf69	Replacement policy cleanup.	2022-02-10 11:42:40 -06:00
Ross Thompson	411997010b	Replacement policy cleanup.	2022-02-10 11:40:10 -06:00
Ross Thompson	382d5fab0f	Cleanup.	2022-02-10 11:27:15 -06:00
Ross Thompson	3a0af5d9e9	Cleanup + critical path optimizations.	2022-02-10 11:11:16 -06:00
Ross Thompson	fc68c2f09a	Cache name clarifications.	2022-02-10 10:50:17 -06:00
Ross Thompson	e00d404154	More cache cleanup.	2022-02-10 10:43:37 -06:00
Ross Thompson	65803ebe98	structural muxes.	2022-02-09 19:36:21 -06:00
Ross Thompson	2a989e6d05	More cache cleanup.	2022-02-09 19:29:15 -06:00
Ross Thompson	3b8ad3f7c7	Cleaned up comments.	2022-02-09 19:21:35 -06:00
Ross Thompson	911ee36b22	Removed all possilbe paths to PreSelAdr from TrapM.	2022-02-09 19:20:10 -06:00
Ross Thompson	01126535db	Annotated the final changes required to move sram address off the critial path.	2022-02-08 18:17:31 -06:00
Ross Thompson	7133e790ea	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 17:52:15 -06:00
Ross Thompson	498388c636	Cache cleanup write enables.	2022-02-08 17:52:09 -06:00
Ross Thompson	8a49ec90d0	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 15:43:18 -06:00
Ross Thompson	e0a605e95d	Cleanup IFU.	2022-02-08 14:54:53 -06:00
Ross Thompson	d1d014bf1d	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 14:47:15 -06:00
Ross Thompson	13561c67bd	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 14:22:19 -06:00
Ross Thompson	cecbb3362d	rv32e works for now. Still need to optimize.	2022-02-08 14:21:55 -06:00
Ross Thompson	39149c618f	Moved some muxes back into the bp.	2022-02-08 14:17:44 -06:00
David Harris	3e16730226	RAM simplification	2022-02-08 20:15:23 +00:00
Ross Thompson	d5d9bb9d4d	Temporary commit which gets the no branch predictor implementation working.	2022-02-08 14:13:55 -06:00
Ross Thompson	3cd067ac6a	Finished merge.	2022-02-08 11:36:24 -06:00
Ross Thompson	492c1473f3	Preparing to make a major change to the cache's write enables.	2022-02-08 09:47:01 -06:00
David Harris	096242a6d8	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
Ross Thompson	190d619940	cachefsm cleanup.	2022-02-07 22:09:56 -06:00
Ross Thompson	ca459a5915	Removed VDWriteEnable.	2022-02-07 21:59:18 -06:00
Ross Thompson	494802b2e1	more partial cleanup of fsm and write enables.	2022-02-07 17:41:56 -06:00
Ross Thompson	23a60d9875	Progress towards simplifying the cache's write enables.	2022-02-07 17:23:09 -06:00
Ross Thompson	fcd43ea004	more cleanup.	2022-02-07 13:29:19 -06:00
Ross Thompson	e72d54ea98	More cachefsm cleanup.	2022-02-07 13:19:37 -06:00
Ross Thompson	a6a7779ec0	More cachefsm cleanup.	2022-02-07 12:30:27 -06:00
Ross Thompson	7f732eb571	More cachefsm cleanup.	2022-02-07 11:16:20 -06:00
Ross Thompson	be67c4d559	More cachefsm cleanup.	2022-02-07 11:12:28 -06:00
Ross Thompson	f1781c6bc8	More cachefsm cleanup.	2022-02-07 10:54:22 -06:00
Ross Thompson	b89ce18473	Cache cleanup.	2022-02-07 10:43:58 -06:00
Ross Thompson	6f4a321d31	More cachfsm cleanup.	2022-02-07 10:33:50 -06:00
David Harris	60c3cdad3a	Reverted cache change	2022-02-07 14:47:20 +00:00
David Harris	c21eb67a07	Cache syntax cleanup	2022-02-07 14:43:24 +00:00
Ross Thompson	8bcaadda6b	More cachefsm cleanup.	2022-02-06 21:50:44 -06:00
Ross Thompson	347e9228f8	started cachefsm cleanup.	2022-02-06 21:39:38 -06:00
David Harris	0feb624bab	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
Ross Thompson	308cc34d6f	Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.	2022-02-04 23:49:07 -06:00
Ross Thompson	1766c0f5ba	Removed unused ports from caches and buses.	2022-02-04 22:52:51 -06:00
Ross Thompson	dce4f8a0e5	Cleanup.	2022-02-04 22:40:51 -06:00
Ross Thompson	53551ab533	Moved the hwdata mux back into the busdp.	2022-02-04 22:39:13 -06:00
Ross Thompson	34cf77797a	Merged together the two sub cache line read muxes. ... One mux was used for loads and the other for eviction.	2022-02-04 22:30:04 -06:00
David Harris	23868a33bc	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
Ross Thompson	c846368537	Moved the sub cache line read logic to lsu/ifu.	2022-02-04 20:42:53 -06:00
Ross Thompson	f6f0539e10	Got separate module for the sub cache line read.	2022-02-04 20:23:09 -06:00
Ross Thompson	ceb2cc30b9	Second optimization of save/restore.	2022-02-04 14:35:12 -06:00