Ross Thompson
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99070127d8
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Added debugging directives to system verilog.
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2021-09-27 13:57:46 -05:00 |
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Ross Thompson
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f2c1ca4bd5
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added support to due partial fpga simulation.
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2021-09-26 15:00:00 -05:00 |
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Ross Thompson
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6dc25e07c2
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Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies
the flash card to dram.
Fixed latch issue in the sd card reader.
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2021-09-26 13:22:23 -05:00 |
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Ross Thompson
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3a15cc7872
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We now have a rough sdc read routine.
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2021-09-25 17:51:38 -05:00 |
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Ross Thompson
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dd9fe60b28
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Write of the SDC address register is correct. The command register is not yet working.
The root problem is the command register needs to be reset at the end of the SDC transaction.
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2021-09-24 18:48:11 -05:00 |
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Ross Thompson
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5663522a3f
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Now have software interacting with the initialization and settting the address register.
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2021-09-24 18:30:26 -05:00 |
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Ross Thompson
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232d4a554f
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Have program which checks for sdc init and issues read, but read done is
not correctly being read back by the software. The error is in how the
sdc indicates busy.
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2021-09-24 15:53:38 -05:00 |
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Ross Thompson
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71e20c7f61
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Fixed lint errors in the SDC.
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2021-09-24 12:38:48 -05:00 |
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Ross Thompson
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af28cfb70c
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Added SDC defines to each config mode.
Added sd_top which is the sd card reader.
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2021-09-24 12:24:30 -05:00 |
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Ross Thompson
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0a33f5fa46
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setup so the sdc does not need to load a model in the imperas test bench.
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2021-09-24 11:30:52 -05:00 |
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Ross Thompson
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78028947bf
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Updated Imperas test bench to work with the SDC reader.
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2021-09-24 11:22:54 -05:00 |
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Ross Thompson
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4256ef82b1
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SDC to ABHLite interface partially done.
Added SDC to adrdec and uncore.
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2021-09-24 10:45:09 -05:00 |
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Ross Thompson
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a182263b1c
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Added clock gater and divider to generate the SDCCLK.
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2021-09-23 17:58:50 -05:00 |
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Ross Thompson
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9ed7a1f494
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Partial implementation of SDC AHBLite interface.
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2021-09-23 17:45:45 -05:00 |
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Ross Thompson
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0f7be5e591
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Started the AHBLite to SDC interface.
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2021-09-22 18:08:38 -05:00 |
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Ross Thompson
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f5905f33d3
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Initial SD Card reader.
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2021-09-22 10:50:29 -05:00 |
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