mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
dd9fe60b28
The root problem is the command register needs to be reset at the end of the SDC transaction. |
||
|---|---|---|
| .. | ||
| tb | ||
| clkdivider.sv | ||
| counter.sv | ||
| crc7_pipo.sv | ||
| crc7_sipo_np_ce.sv | ||
| crc16_sipo_np_ce.sv | ||
| piso_generic_ce.sv | ||
| regfile_p2r1w1_nibo.sv | ||
| regfile_p2r1w1bwen.sv | ||
| sd_clk_fsm.sv | ||
| sd_cmd_fsm.sv | ||
| sd_dat_fsm.sv | ||
| sd_top.sv | ||
| SDC.sv | ||
| simple_timer.sv | ||
| sipo_generic_ce.sv | ||
| up_down_counter.sv | ||