Ross Thompson
b621eb78fb
Updated debug2 ila signal names.
2022-01-28 11:43:49 -06:00
Ross Thompson
728e46a794
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
Ross Thompson
71eb1df492
Added comport.setup to remind how to configure com port for xilinx fpga.
...
Added load-deadlock.tsm to trigger load operation deadlock.
2022-01-25 14:54:38 -06:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
f7f3882cb8
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
Ross Thompson
88d5edaf13
Added advanced Vivado debug scripts.
2022-01-07 17:56:40 -06:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
Ross Thompson
79ec4161b6
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
9f798250ea
Oups missed files in the last commit.
2021-12-15 10:25:08 -06:00
Ross Thompson
f061a26411
Cleaned up fpga synthesis script.
2021-12-13 18:26:54 -06:00
Ross Thompson
bb79f70a63
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
3d829dbbd3
Fixed two issues.
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First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
Ross Thompson
517cae796c
Fixed more constraint issues in fpga.
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Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
Ross Thompson
cb744280c3
Fixed a bunch of fpga issues.
2021-12-03 17:47:54 -06:00
Ross Thompson
35dd1b5c9f
Improved FPGA makefile and fixed timing constraints in clock converter.
2021-12-03 10:05:13 -06:00
Ross Thompson
5d4051d1c2
Constraints for fpga are still wrong.
2021-12-02 14:23:21 -06:00
Ross Thompson
2cfbdb1c47
Added tcl commands to build the implementation.
2021-12-02 10:17:30 -06:00
Ross Thompson
6a228ade04
Got fpga synthesis running from scripts.
2021-12-01 16:59:04 -06:00
Ross Thompson
7f52d86980
Added make clean to fpga IP generator.
2021-11-29 18:42:28 -06:00
Ross Thompson
1117b90f40
Created Makefile to manage IP generation.
2021-11-29 18:33:58 -06:00
Ross Thompson
84116a756e
Added final IP generator script (proc_sys_reset).
2021-11-29 17:43:47 -06:00
Ross Thompson
ce91732856
Added ddr4 generator script.
2021-11-29 15:56:57 -06:00
Ross Thompson
9a0bf54840
Created tcl scripts to build 2 of the 4 xilinx IP.
2021-11-29 11:26:08 -06:00
