Daniel Torres
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95fdd408ee
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commiting current changes to riscof wally tests
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2022-07-22 11:14:04 -07:00 |
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Katherine Parry
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7268b4b334
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removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Katherine Parry
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18d7fee541
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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DTowersM
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fe7d03a3da
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added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
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2022-07-11 21:13:09 +00:00 |
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Katherine Parry
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97e7e619d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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David Harris
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8be1dafbd6
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Removed testbench code that ignores mismatch on zero signatures
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2022-07-08 09:17:31 +00:00 |
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David Harris
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f865994ba1
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fixing port errors
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2022-07-07 21:57:10 +00:00 |
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David Harris
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f5bdbbe219
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Removed sig4 spurious message from testbench
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2022-07-05 03:27:14 +00:00 |
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Daniel Torres
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2ae22ac6cb
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added changes to testbench, tests and riscof for additional riscof compatability
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2022-06-29 12:23:40 -07:00 |
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slmnemo
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80a57d0469
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-21 02:16:26 -07:00 |
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slmnemo
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b2cea45de0
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Added rudimentary GPIO test according to testplans in chapter 15
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2022-06-21 02:16:21 -07:00 |
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Katherine Parry
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03d823f5d7
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added fld in rv32 - needs testing
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2022-06-20 22:53:13 +00:00 |
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Daniel Torres
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397783812d
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embench and testbench now support running both O2 and Os build variations without overwriting one another
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2022-06-17 21:15:42 -07:00 |
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Daniel Torres
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1d4c543f71
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arch tests now run on spike and sail and compare signatures during build
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2022-06-17 20:53:15 -07:00 |
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Daniel Torres
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0ede7c412e
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removed old code from makefile, simplified code in testbench
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2022-06-17 15:13:38 -07:00 |
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Daniel Torres
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475220a5ff
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arch bug fixes and testbench changes
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2022-06-17 15:07:16 -07:00 |
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Katherine Parry
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5f7072bd96
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postprocessing unit created and passing all tests
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2022-06-13 22:47:51 +00:00 |
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slmnemo
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a5aa75e5de
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Merge branch 'main' into cacheburstmode
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2022-06-08 02:21:33 +00:00 |
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DTowersM
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1d41e98504
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 23:58:58 +00:00 |
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DTowersM
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3d654fd481
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modified testbench.sv- now works with coremark
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2022-06-07 23:58:50 +00:00 |
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DTowersM
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930c806753
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cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
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2022-06-07 23:27:54 +00:00 |
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DTowersM
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4cadf139a6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 06:03:19 +00:00 |
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DTowersM
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fbfae61ba8
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added support for 64 bit rv tests
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2022-06-07 06:02:23 +00:00 |
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DTowersM
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23d524b439
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testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh
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2022-06-03 22:07:14 +00:00 |
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David Harris
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9cd6b309b4
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Cleaned up test cases in testbench
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2022-06-02 08:44:28 -07:00 |
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DTowersM
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d3c8ee7154
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added support for embench post processing to testbench.sv
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2022-06-01 21:00:44 +00:00 |
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DTowersM
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2088c0cd7c
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added testbench.sv support for embench tests, test output still WIP
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2022-05-31 20:13:32 +00:00 |
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DTowersM
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a983791d64
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fixed indent spacing (cosmetic change)
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2022-05-26 19:04:21 +00:00 |
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slmnemo
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87cfd62e19
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Added line to testbench to prevent annoying burst sizes
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2022-05-25 17:29:45 -07:00 |
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slmnemo
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5a9e3a852a
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see commit 9042cc3c
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2022-05-25 17:10:59 -07:00 |
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slmnemo
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d43d340e31
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added logic to prevent cache line length from exceeding the max size of a burst.
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2022-05-25 17:03:15 -07:00 |
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slmnemo
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a5d5bd272b
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changes suggested by ben, hopefully fixing buildroot (which is now not running)
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2022-05-20 18:42:38 -07:00 |
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slmnemo
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ba572b46f4
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Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature.
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2022-05-17 01:04:13 +00:00 |
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slmnemo
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ede0a3237d
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quit
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2022-05-17 01:03:09 +00:00 |
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David Harris
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730bcac6ba
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Partitioned privileged pipeline registers into module
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2022-05-12 20:45:45 +00:00 |
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David Harris
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de5b61291f
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Experiments with prefix comparator; minor fixes in WFI and testbench warnings
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2022-04-17 21:43:12 +00:00 |
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Ross Thompson
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1993069986
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
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fc2b4453ec
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
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de2672231d
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Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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Ross Thompson
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d68446cf92
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Added new asserts to testbench.
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2022-03-11 15:41:53 -06:00 |
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bbracker
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443dd40ea8
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remove imperas32p tests
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2022-03-04 00:06:18 +00:00 |
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bbracker
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d7b8c9d877
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add rv32a tests to regression
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2022-03-02 17:54:55 +00:00 |
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bbracker
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4f22a55dd4
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add LRSC test and add wally64a to regression
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2022-03-02 07:09:37 +00:00 |
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bbracker
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d620fb4442
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deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
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2022-03-01 00:37:46 +00:00 |
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bbracker
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6caa97bb26
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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David Harris
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e5097e67d4
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Fixed TIM tests; rv32e test still failing
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2022-02-08 15:24:37 +00:00 |
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David Harris
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e9a519a228
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Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail
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2022-02-08 12:40:02 +00:00 |
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David Harris
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096242a6d8
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Merged TIM and regular testbenches. RV32e now working and back in regression.
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2022-02-08 12:18:13 +00:00 |
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David Harris
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23868a33bc
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Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
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2022-02-05 04:16:18 +00:00 |
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David Harris
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16b5fee795
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RV32e tests
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2022-02-04 14:30:36 +00:00 |
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