Ross Thompson
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93829ce509
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Success! We have some instructions comparing across the FPGA and IDV!
However I'm still losing ethernet frames.
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2024-06-17 13:41:40 -07:00 |
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Ross Thompson
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598770da51
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Getting much closer to a working version.
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2024-06-17 12:37:10 -07:00 |
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Ross Thompson
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cccb40e4b5
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Got the tracer not overrunning ethernet buffers so frames are not being dropped.
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2024-06-17 09:16:24 -07:00 |
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Ross Thompson
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82b54c0887
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Got IDV properly initalized.
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2024-06-17 09:15:59 -07:00 |
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Ross Thompson
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47523c97ac
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Getting closer to figuring out the lost ethernet frame bugs.
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2024-06-13 15:46:54 -07:00 |
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Ross Thompson
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c9f51df34a
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Fixed bug in rvvi reset.
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2024-06-12 14:47:32 -07:00 |
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Ross Thompson
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323dbd348e
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Progress.
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2024-06-12 12:54:21 -07:00 |
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Ross Thompson
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f5d4db68b1
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Modified rvvidaemon to populate a struct with all the relavent fields.
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2024-06-12 08:56:16 -07:00 |
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Ross Thompson
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3e7d07dfb6
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Better.
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2024-06-11 17:14:59 -07:00 |
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Ross Thompson
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8bce2fc739
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Getting closer.
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2024-06-11 16:21:53 -07:00 |
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Ross Thompson
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c9f3da51cb
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getting closer to full reconstruction of rvvi.
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2024-06-11 15:35:35 -07:00 |
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Ross Thompson
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3d9f796f21
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Better parsing of rvvi.
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2024-06-11 14:36:34 -07:00 |
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Ross Thompson
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563980443a
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Merge branch 'main' into rvvi
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2024-06-10 18:10:23 -07:00 |
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Ross Thompson
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49912589f5
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Added rvviApi.h to rvvidaemon.
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2024-06-10 17:57:24 -07:00 |
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Ross Thompson
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e16cf9d739
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Added Makefile to compile rvvidaemon
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2024-06-10 16:56:53 -07:00 |
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Rose Thompson
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72c1374d9c
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Minor code cleanup.
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2024-06-04 15:11:57 -05:00 |
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Rose Thompson
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f0ed780745
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progress.
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2024-06-04 15:11:03 -05:00 |
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Rose Thompson
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07d66c246c
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Update.
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2024-06-04 11:59:17 -05:00 |
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Rose Thompson
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08ff88f428
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On the way towards complete reconstruction of the RVVI trace.
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2024-06-04 11:47:46 -05:00 |
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Rose Thompson
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fc62f80407
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Closer to fully working hardware tracer.
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2024-06-04 11:31:05 -05:00 |
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Rose Thompson
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80f98b3223
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now have a working ethernet daemon to collect frames and partially decode into RVVI.
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2024-06-04 10:20:51 -05:00 |
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Rose Thompson
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dc904cdbbb
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The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field.
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2024-06-03 18:10:25 -05:00 |
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Rose Thompson
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0ca10e7ee2
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Last of the branch predictor signal name updates.
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2024-06-02 17:01:51 -05:00 |
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Rose Thompson
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04744032d8
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Updated more signal names to match book.
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2024-06-02 16:59:11 -05:00 |
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Rose Thompson
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b45b7ff7d6
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Signal name changes to match book.
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2024-06-02 16:32:25 -05:00 |
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Rose Thompson
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731e1fe08f
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Updated spill logic to reflect changes in textbook.
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2024-06-02 15:48:42 -05:00 |
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Rose Thompson
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3da62558ec
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Updated readme.
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2024-06-01 11:12:30 -05:00 |
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Rose Thompson
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2382677f8f
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Got the directory mode wsim working!
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2024-06-01 10:56:37 -05:00 |
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Rose Thompson
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224b8469ab
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Updated readme to reflect changes to wsim.
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2024-06-01 09:58:10 -05:00 |
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Rose Thompson
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a78093274c
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Simplified wsim so it automatically figures out if the second parameter is a testsuite or an elf file.
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2024-06-01 09:56:50 -05:00 |
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Rose Thompson
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2a6c5a158f
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-06-01 09:50:18 -05:00 |
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Rose Thompson
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a830bd57f0
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Have to reverse the byte order for ethernet frame length.
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2024-05-31 17:46:43 -05:00 |
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Rose Thompson
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e05ebc30b8
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Almost worked out the bugs in packetizer.
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2024-05-31 16:48:41 -05:00 |
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Rose Thompson
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9ed78b5f08
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Merge pull request #818 from JacobPease/main
Added true bootloader to fpga/zsbl directory.
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2024-05-31 15:34:08 -05:00 |
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Jacob Pease
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7a417d7a6c
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Added true bootloader to fpga/zsbl directory.
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2024-05-31 15:28:25 -05:00 |
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Rose Thompson
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0dccc6051d
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draft of receiving code to unpack the ethernet frames into rvvi.
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2024-05-31 13:55:25 -05:00 |
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Rose Thompson
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1df3e5239a
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This is great. The FPGA is able to send ethernet frames consisting of the RVVI data to the host computer.
wireshark is able to capture the frames and they match the expected data!
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2024-05-30 17:57:28 -05:00 |
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Rose Thompson
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6a4c8667df
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Added new signals to ILA to debug the RVVI tracer.
The tracer appears to be stuck and the CPU is never getting out of (into reset).
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2024-05-30 16:43:25 -05:00 |
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Rose Thompson
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ca90c6ba48
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Added the ethernet files. These are part of another repo.
We should remove before mainlining this.
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2024-05-30 16:33:49 -05:00 |
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Rose Thompson
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38ddbf860e
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Fixed bug with mmcm not generating the 4th clock.
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2024-05-30 16:19:28 -05:00 |
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Rose Thompson
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24ba51370a
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Merge pull request #817 from JacobPease/main
The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
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2024-05-30 16:16:05 -05:00 |
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Jacob Pease
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3f7659c8ad
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Removed old fpgaTop.v file.
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2024-05-30 16:15:19 -05:00 |
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Jacob Pease
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6bf43ebe61
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-05-30 15:48:31 -05:00 |
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Jacob Pease
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7ecd1c7d5f
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The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
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2024-05-30 15:48:27 -05:00 |
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Rose Thompson
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9703055758
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The FPGA is synthesizing with the rvvi and ethernet hardware.
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2024-05-30 15:37:17 -05:00 |
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Rose Thompson
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f4626d5b06
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Fixed bug so that wsim can start logging after a given number of instructions.
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2024-05-29 14:50:09 -05:00 |
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Rose Thompson
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84946919a4
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Changed name CacheWriteData to WriteData.
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2024-05-28 18:00:39 -05:00 |
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Rose Thompson
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273b41df99
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Changed name of cache parameter NUMLINES to NUMSETS to better match book.
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2024-05-28 17:55:43 -05:00 |
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David Harris
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44f25186c6
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Merge pull request #816 from ross144/main
Merges support for functional coverage into wally.do and testbench.sv
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2024-05-28 21:54:37 +02:00 |
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Rose Thompson
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a88d5f403b
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Functional coverage works with wally.do
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2024-05-28 14:02:54 -05:00 |
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