DTowersM
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930c806753
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cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
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2022-06-07 23:27:54 +00:00 |
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DTowersM
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4cadf139a6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 06:03:19 +00:00 |
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DTowersM
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fbfae61ba8
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added support for 64 bit rv tests
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2022-06-07 06:02:23 +00:00 |
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DTowersM
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23d524b439
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testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh
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2022-06-03 22:07:14 +00:00 |
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David Harris
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9cd6b309b4
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Cleaned up test cases in testbench
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2022-06-02 08:44:28 -07:00 |
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DTowersM
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d3c8ee7154
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added support for embench post processing to testbench.sv
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2022-06-01 21:00:44 +00:00 |
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DTowersM
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2088c0cd7c
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added testbench.sv support for embench tests, test output still WIP
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2022-05-31 20:13:32 +00:00 |
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DTowersM
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a983791d64
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fixed indent spacing (cosmetic change)
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2022-05-26 19:04:21 +00:00 |
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slmnemo
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5a9e3a852a
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see commit 9042cc3c
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2022-05-25 17:10:59 -07:00 |
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slmnemo
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d43d340e31
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added logic to prevent cache line length from exceeding the max size of a burst.
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2022-05-25 17:03:15 -07:00 |
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slmnemo
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a5d5bd272b
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changes suggested by ben, hopefully fixing buildroot (which is now not running)
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2022-05-20 18:42:38 -07:00 |
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slmnemo
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ba572b46f4
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Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature.
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2022-05-17 01:04:13 +00:00 |
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slmnemo
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ede0a3237d
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quit
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2022-05-17 01:03:09 +00:00 |
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David Harris
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730bcac6ba
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Partitioned privileged pipeline registers into module
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2022-05-12 20:45:45 +00:00 |
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David Harris
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de5b61291f
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Experiments with prefix comparator; minor fixes in WFI and testbench warnings
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2022-04-17 21:43:12 +00:00 |
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Ross Thompson
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1993069986
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
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fc2b4453ec
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
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de2672231d
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Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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Ross Thompson
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d68446cf92
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Added new asserts to testbench.
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2022-03-11 15:41:53 -06:00 |
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bbracker
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443dd40ea8
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remove imperas32p tests
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2022-03-04 00:06:18 +00:00 |
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bbracker
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d7b8c9d877
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add rv32a tests to regression
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2022-03-02 17:54:55 +00:00 |
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bbracker
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4f22a55dd4
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add LRSC test and add wally64a to regression
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2022-03-02 07:09:37 +00:00 |
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bbracker
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d620fb4442
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deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
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2022-03-01 00:37:46 +00:00 |
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bbracker
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6caa97bb26
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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David Harris
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e5097e67d4
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Fixed TIM tests; rv32e test still failing
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2022-02-08 15:24:37 +00:00 |
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David Harris
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e9a519a228
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Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail
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2022-02-08 12:40:02 +00:00 |
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David Harris
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096242a6d8
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Merged TIM and regular testbenches. RV32e now working and back in regression.
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2022-02-08 12:18:13 +00:00 |
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David Harris
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23868a33bc
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Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
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2022-02-05 04:16:18 +00:00 |
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David Harris
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16b5fee795
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RV32e tests
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2022-02-04 14:30:36 +00:00 |
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David Harris
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e92461159d
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cache cleanup
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2022-02-03 15:36:11 +00:00 |
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David Harris
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9e0055cbb9
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More config file cleanup; 32ic tests broken
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2022-02-03 01:08:34 +00:00 |
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David Harris
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bdf1a8ba73
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changed DMEM and IMEM configurations to support BUS/TIM/CACHE
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2022-02-03 00:41:09 +00:00 |
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Ross Thompson
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2f7cf2bc7f
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Fixed testbench so coremark stops.
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2022-02-02 11:37:48 -06:00 |
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Ross Thompson
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ae36931bb2
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Added correct stop condition for coremark.
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2022-02-02 09:53:51 -06:00 |
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Ross Thompson
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138b17a399
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Setup the main regression test to be able to handle coremark.
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2022-02-01 17:00:11 -06:00 |
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David Harris
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62e5c7fd13
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Comments in LSU code about restructuring
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2022-01-27 15:53:59 +00:00 |
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David Harris
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ca1f7ce5d3
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Renamed wallypipelinedhart to wallypipelinedcore
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2022-01-20 16:02:08 +00:00 |
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David Harris
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5842d780a7
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Defined rv32e and rv32emc configs
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2022-01-17 14:01:01 +00:00 |
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David Harris
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f7f3882cb8
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Moved Dcache into bus block
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2022-01-15 00:39:07 +00:00 |
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David Harris
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37bf5347cf
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LSU cleanup
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2022-01-14 23:55:27 +00:00 |
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Ross Thompson
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9f7e3f147b
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Partial local dtim in lsu configuration.
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2022-01-13 17:50:31 -06:00 |
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David Harris
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453a794f86
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Testbench directory cleanup
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2022-01-07 17:02:16 +00:00 |
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David Harris
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3d2671a8b0
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Reformatted MIT license to 95 characters
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2022-01-07 12:58:40 +00:00 |
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David Harris
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d17a305538
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Finished removing generate statements
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2022-01-05 16:41:17 +00:00 |
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Ross Thompson
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888a60d8d6
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Switched block for line in caches.
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2022-01-04 22:08:18 -06:00 |
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David Harris
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9ddc6db0a6
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Removed imperas mmu tests; using wallypriv instead
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2022-01-04 23:14:53 +00:00 |
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David Harris
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115287adc8
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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