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109 Commits

Author SHA1 Message Date
Ross Thompson
ff7dc4f34a fpga constraints updates 2023-02-07 15:22:14 -06:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
Ross Thompson
2fc47bab9c More fixes for the debug2.xdc constraints. 2023-01-20 20:48:19 -06:00
Ross Thompson
61efb22db1 More fixes to fpga ila debugger. 2023-01-20 20:28:21 -06:00
Ross Thompson
e28ea2d630 Fixed fpga constraints. 2023-01-20 20:18:04 -06:00
Ross Thompson
0ed9811e31 Updated fpga constraints. 2023-01-20 20:16:33 -06:00
Ross Thompson
4ccea17648 Added license and comments to new script. 2023-01-20 19:50:33 -06:00
Ross Thompson
9c83b2dff5 Updated ignore to exclude copied files. 2023-01-20 19:47:33 -06:00
Ross Thompson
25bd2e4670 Removed mark_debug vivado directive from source code. 
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
 2023-01-20 19:43:18 -06:00
Ross Thompson
6ccb3a0147 Test commit. 2023-01-20 17:27:09 -06:00
Ross Thompson
11c6106022 Repaired fpga debugger. 2023-01-20 15:26:52 -06:00
Ross Thompson
5b740fbf60 Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
e0ec45489a Updated constraints to remove DivBusyE. 2022-12-30 10:51:35 -06:00
Ross Thompson
138c3542db Updated fpga constraints. 2022-12-24 10:21:16 -06:00
Ross Thompson
b5a85b55f1 Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
6b105bd217 Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
15042fc856 Updated fpga constraints. 2022-12-21 14:50:01 -06:00
Ross Thompson
13beda7d0c Updated vcu118 piniout. 2022-12-18 14:00:10 -06:00
Ross Thompson
3ee6ed8542 Updated fpga constraints 2022-12-15 16:45:55 -06:00
rachanaerra
10ff69efc1 updated constraints file 2022-12-05 15:05:21 -06:00
Ross Thompson
e99a424ddc Updated top level fpga file. 2022-11-18 11:10:45 -06:00
Ross Thompson
70d7fca750 Updated fpga wave configuration. 2022-11-16 15:57:19 -06:00
Ross Thompson
cf00f85456 Updated vcu118 constraints to run cpu at 38.43Mhz. 2022-11-15 10:19:38 -06:00
Ross Thompson
cc80f1f7b2 Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s). 
Increased CPU clock speed from 30 Mhz to 35 Mhz.
 2022-11-11 15:33:03 -06:00
Ross Thompson
30b2bd263c Updates to fpga constraints. 2022-11-09 13:52:36 -06:00
Ross Thompson
5c49cc4dd0 Fixed bug with fpga makefile. 2022-11-07 09:20:05 -06:00
Jacob Pease
160ca366c8 Added PLIC signals for debugging on FPGA. 2022-10-25 13:57:09 -05:00
Ross Thompson
9ba487c323 Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
92ace4d8f7 Forget to include updated xdc file. 2022-10-24 13:51:21 -05:00
Ross Thompson
a008c61939 Updated debug2.xdc for interlock fsm changes. 2022-10-19 17:34:47 -05:00
Ross Thompson
92accfb1a6 Updated uart settings and fpga wave config. 2022-10-18 15:05:33 -05:00
Ross Thompson
2d063bbb2d Updated constraints file to work with alternate uart. 2022-10-04 17:35:44 -05:00
Ross Thompson
16e10a4c5b added new constraints for fpga. 2022-09-17 22:20:06 -05:00
Ross Thompson
787f5bcccb Fixed fpga debug constraints. 2022-09-03 17:36:29 -05:00
Ross Thompson
53995c2ed3 update to fpga wave. 2022-09-02 15:54:54 -05:00
Ross Thompson
5d2b299182 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
4d60d9a840 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
Ross Thompson
01a7718471 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
701324eeb8 Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
Ross Thompson
8180d1ade4 Updated fpga debugger to latest RTL version. 2022-08-19 17:13:36 -05:00
Ross Thompson
8b2491c169 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-19 16:39:28 -05:00
Ross Thompson
83bca570ae Modified debugger for updated rtl. 2022-06-04 14:39:55 -05:00
Ross Thompson
1318f702cf Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Ross Thompson
db85afcd2d Added more plic debugging signals. 2022-05-21 14:04:08 -05:00
Ross Thompson
6cae5aa88f Updated the fpga constraints. 2022-05-21 13:32:03 -05:00
Ross Thompson
9079e67aae Updated fpga debugger. 2022-05-17 23:04:01 -05:00
Ross Thompson
51add16def Updated debugger constraints. 2022-05-09 10:19:25 -05:00
Ross Thompson
c045e3afd8 Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
82356342f0 Added another GPR to debugger. 2022-04-17 18:12:05 -05:00
Ross Thompson
c16dec88de Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00