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1,401 Commits 4 Branches 2 Tags 53 MiB
8e966b37f2
Commit Graph

739 Commits

Author SHA1 Message Date
David Harris
8e966b37f2 hptw: renamed ADRE to ADR 2021-07-17 14:02:59 -04:00
David Harris
95d49e4e9b hptw: replaced PreviousWalkerState with a PageType FSM 2021-07-17 13:54:58 -04:00
David Harris
964f0d9f53 hptw: removed ITLBMissFQ 2021-07-17 13:44:08 -04:00
David Harris
9741b01465 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
David Harris
ee784c19a5 hptw: Simplifed out AnyTLBMiss 2021-07-17 12:07:51 -04:00
David Harris
40989c4e3d hptw: Renamed Memstore to MemWrite 2021-07-17 12:01:43 -04:00
David Harris
ddd9110f7b hptw: Merged RV32/64 FSMs 2021-07-17 11:55:24 -04:00
David Harris
36a8d23222 hptw: FSM simplification 2021-07-17 11:41:43 -04:00
David Harris
6d28f3fe08 hptw: default state should be unreachable 2021-07-17 11:33:16 -04:00
David Harris
ef83a44c4d hptw: factored Misaligned 2021-07-17 11:31:16 -04:00
David Harris
e3b26b7b23 hptw: factored HPTWRead 2021-07-17 11:25:59 -04:00
David Harris
1bbc932bfd hptw: factored HPTWRead 2021-07-17 11:25:52 -04:00
David Harris
37cc2ca30f hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
1595e4f992 HPTW: more cleanup 2021-07-17 04:55:01 -04:00
David Harris
b74f3b14ec HPTW: factored out DTLBWrite/ITLBWrite 2021-07-17 04:44:23 -04:00
David Harris
9775294a6f HPTW: factored out PageTableENtry 2021-07-17 04:40:01 -04:00
David Harris
f168bd6749 more cleaning up FSM 2021-07-17 04:35:51 -04:00
David Harris
e2600bc55d cleaning up FSM 2021-07-17 04:26:41 -04:00
David Harris
52a7dd9ac0 Simplify FSM 2021-07-17 04:12:31 -04:00
David Harris
31a3b39e5c Pulled TranslationPAdr mux out of HPTW FSM 2021-07-17 04:06:26 -04:00
David Harris
7eb03c2ff6 Simplified bad PTE detection 2021-07-17 03:30:17 -04:00
David Harris
b8ee8a8ce0 Pulled out shared PTEReg 2021-07-17 03:21:09 -04:00
David Harris
d3974fafdd Flip-flop clean-up 2021-07-17 03:15:47 -04:00
David Harris
de72dff382 Flip-flop clean-up 2021-07-17 03:12:24 -04:00
David Harris
a5ac606dda Flip-flop clean-up 2021-07-17 03:10:17 -04:00
David Harris
2b0f8e9cf6 Started pagetablewalker cleanup: combined state flops shared for both RV versions 2021-07-17 02:53:52 -04:00
David Harris
fe8910437a Replaced separate PageTypeF and PageTypeM with common PageType 2021-07-17 02:31:23 -04:00
David Harris
622a14cbdd Removed more unused signals from ahblite 2021-07-17 02:21:54 -04:00
David Harris
52fcc47cdf Removed rest of HRDATAW from ahblite 2021-07-17 02:15:24 -04:00
David Harris
1d171d7ea6 Commented out HRDATAW logic in ebu 2021-07-17 02:10:57 -04:00
David Harris
d6f859da18 renamed or_rows.sv 2021-07-16 20:17:03 -04:00
Ross Thompson
e9649eb1f5 Made furture progress in the mmu tests. 2021-07-16 15:56:06 -05:00
Ross Thompson
abce241f68 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
d3715acf2d Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00
Ross Thompson
5ca7dc619c Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues. 2021-07-16 11:12:57 -05:00
Kip Macsai-Goren
ba5bb12e26 Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction. 2021-07-15 18:30:29 -04:00
Ross Thompson
96aa106852 Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
4549a9f1c9 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
c39a228266 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
c954fb510b Renamed DCacheStall to LSUStall in hart and hazard. 
Added missing logic in lsu.
 2021-07-15 10:16:16 -05:00
Ross Thompson
f234875779 dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
6163629204 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
701ea38964 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
d41c9d5ad9 Added d cache StallW checks for any time the cache wants to go to STATE_READY. 2021-07-14 17:25:50 -05:00
Ross Thompson
d3a1a2c90a Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Katherine Parry
f8b76082e4 fpu unpacking unit created 2021-07-14 17:56:49 -04:00
Ross Thompson
771c7ff130 Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
1d7aa27316 Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled. 2021-07-14 15:47:38 -05:00
Ross Thompson
3092e5acdf Forgot to include one hot decoder. 2021-07-14 15:46:52 -05:00
Ross Thompson
e17de4eb11 Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. 
This solves the committedM issue.
 2021-07-14 15:00:33 -05:00