17 Commits

Author	SHA1	Message	Date
Ross Thompson	8e51935082	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Ross Thompson	f1f7884e10	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-10 15:37:02 -06:00
Ross Thompson	7b7cacbaf0	Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.	2021-03-10 11:00:51 -06:00
David Harris	bea8ac6d59	WALLY-LRSC atomic test passing	2021-03-09 09:28:25 -05:00
Ross Thompson	9a93193d6a	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
Ross Thompson	619bbd9d83	Merge branch 'bp' into main ... Concerns: 1. I don't think the correct data buses are going to the multiplier. 2. I'm not sure the FlushF signal is correct.	2021-03-04 13:35:46 -06:00
David Harris	73920282af	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
Teo Ene	8491deb1a9	Changed .do file back to run all	2021-02-25 09:58:54 -06:00
Ross Thompson	bbe0db3ebe	Integrated the branch predictor into the hardward. Not yet working.	2021-02-17 22:19:17 -06:00
David Harris	842c374de9	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
David Harris	9511dcac84	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	d104e5a4be	Moving data memory to uncore	2021-01-29 15:37:51 -05:00
David Harris	37a58cea17	Repartitioned with Instruction Fetch Unit, Integer Execution Unit	2021-01-27 22:49:47 -05:00
David Harris	4318629b32	Repartitioned datapath and controller into ieu	2021-01-27 06:40:26 -05:00
David Harris	bf07ec92b5	Added test configurations	2021-01-25 11:28:43 -05:00