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1447 Commits

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Author SHA1 Message Date
David Harris
ee784c19a5 hptw: Simplifed out AnyTLBMiss 2021-07-17 12:07:51 -04:00
David Harris
40989c4e3d hptw: Renamed Memstore to MemWrite 2021-07-17 12:01:43 -04:00
David Harris
ddd9110f7b hptw: Merged RV32/64 FSMs 2021-07-17 11:55:24 -04:00
David Harris
36a8d23222 hptw: FSM simplification 2021-07-17 11:41:43 -04:00
David Harris
6d28f3fe08 hptw: default state should be unreachable 2021-07-17 11:33:16 -04:00
David Harris
ef83a44c4d hptw: factored Misaligned 2021-07-17 11:31:16 -04:00
David Harris
e3b26b7b23 hptw: factored HPTWRead 2021-07-17 11:25:59 -04:00
David Harris
1bbc932bfd hptw: factored HPTWRead 2021-07-17 11:25:52 -04:00
David Harris
37cc2ca30f hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
1595e4f992 HPTW: more cleanup 2021-07-17 04:55:01 -04:00
David Harris
b74f3b14ec HPTW: factored out DTLBWrite/ITLBWrite 2021-07-17 04:44:23 -04:00
David Harris
9775294a6f HPTW: factored out PageTableENtry 2021-07-17 04:40:01 -04:00
David Harris
f168bd6749 more cleaning up FSM 2021-07-17 04:35:51 -04:00
David Harris
e2600bc55d cleaning up FSM 2021-07-17 04:26:41 -04:00
David Harris
e1d56c10ba merged hptw 2021-07-17 04:19:37 -04:00
David Harris
52a7dd9ac0 Simplify FSM 2021-07-17 04:12:31 -04:00
David Harris
31a3b39e5c Pulled TranslationPAdr mux out of HPTW FSM 2021-07-17 04:06:26 -04:00
David Harris
7eb03c2ff6 Simplified bad PTE detection 2021-07-17 03:30:17 -04:00
David Harris
b8ee8a8ce0 Pulled out shared PTEReg 2021-07-17 03:21:09 -04:00
David Harris
d3974fafdd Flip-flop clean-up 2021-07-17 03:15:47 -04:00
David Harris
de72dff382 Flip-flop clean-up 2021-07-17 03:12:24 -04:00
David Harris
a5ac606dda Flip-flop clean-up 2021-07-17 03:10:17 -04:00
David Harris
5eee2f9f4f Flip-flop clean-up 2021-07-17 02:59:35 -04:00
David Harris
2b0f8e9cf6 Started pagetablewalker cleanup: combined state flops shared for both RV versions 2021-07-17 02:53:52 -04:00
David Harris
fe8910437a Replaced separate PageTypeF and PageTypeM with common PageType 2021-07-17 02:31:23 -04:00
David Harris
622a14cbdd Removed more unused signals from ahblite 2021-07-17 02:21:54 -04:00
David Harris
52fcc47cdf Removed rest of HRDATAW from ahblite 2021-07-17 02:15:24 -04:00
David Harris
1d171d7ea6 Commented out HRDATAW logic in ebu 2021-07-17 02:10:57 -04:00
David Harris
d6f859da18 renamed or_rows.sv 2021-07-16 20:17:03 -04:00
David Harris
f69393f197 Reduced size of physical memory by 16 for performance 2021-07-16 20:10:12 -04:00
Kip Macsai-Goren
3d14d573a0 included virtual memory tests in testbench 2021-07-16 17:57:24 -04:00
Kip Macsai-Goren
6988a89ce6 removed old unused tests and outputs 2021-07-16 17:46:51 -04:00
Kip Macsai-Goren
1f7e94f46a added backup reference output for sv32 2021-07-16 17:46:16 -04:00
Kip Macsai-Goren
06db4c08ef removed execution tests until fences are implemented 2021-07-16 17:45:54 -04:00
Kip Macsai-Goren
e62b22a72d added backup output files for when execution tests are possible 2021-07-16 17:25:40 -04:00
Kip Macsai-Goren
b7b7c170ec removed execution tests until fences are implemented 2021-07-16 17:24:59 -04:00
Ross Thompson
8d4432e9a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-16 15:59:13 -05:00
Kip Macsai-Goren
e4f6063b6f More fixes to bring physical address into dtim range 2021-07-16 16:58:28 -04:00
Ross Thompson
e9649eb1f5 Made furture progress in the mmu tests. 2021-07-16 15:56:06 -05:00
Kip Macsai-Goren
7e2d150a57 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-16 16:05:50 -04:00
Ross Thompson
0c9dad2db6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-16 15:04:38 -05:00
Ross Thompson
965f34d78f Added guide for Ben to do linux conversion. 2021-07-16 15:04:30 -05:00
Kip Macsai-Goren
6aeb6c2123 removed exectution tests that intentionally fail as well until fences are implemented. 2021-07-16 15:47:08 -04:00
Kip Macsai-Goren
81ea24d25b removed execution tests that are supposed to pass until fences are implemented. 2021-07-16 15:32:13 -04:00
Ross Thompson
abce241f68 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
6ab7cd0f4d Updated the config so the tim has a bigger range. 2021-07-16 12:35:00 -05:00
Ross Thompson
bebc7cc5e3 Updated wave file. 2021-07-16 12:34:37 -05:00
Ross Thompson
d3715acf2d Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00
bbracker
e51ab63a86 reduce number of UART ports to 1 2021-07-16 12:42:29 -04:00
bbracker
c7712d035b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-16 12:27:25 -04:00