mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
merged hptw
This commit is contained in:
David Harris
commit
e1d56c10ba
@ -78,7 +78,7 @@ module pagetablewalker
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logic [`PPN_BITS-1:0] BasePageTablePPN;
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logic [`XLEN-1:0] TranslationVAdr;
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logic [`XLEN-1:0] SavedPTE, CurrentPTE;
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logic [`XLEN-1:0] CurrentPTE;
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logic [`PA_BITS-1:0] TranslationPAdr;
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logic [`PPN_BITS-1:0] CurrentPPN;
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logic [`SVMODE_BITS-1:0] SvMode;
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@ -88,7 +88,7 @@ module pagetablewalker
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logic Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid;
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// PTE descriptions
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logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE;
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logic ValidPTE, ADPageFault, MegapageMisaligned, BadMegapage, LeafPTE;
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// Outputs of walker
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logic [`XLEN-1:0] PageTableEntry;
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@ -120,8 +120,6 @@ module pagetablewalker
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
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@ -133,28 +131,17 @@ module pagetablewalker
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assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
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flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);
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flopenrc #(2) TLBMissMReg(clk, reset, StartWalk | EndWalk, EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ});
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/* .reset(reset),
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.en(StartWalk | EndWalk),
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.clear(EndWalk),
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.d(DTLBMissM),
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.q(DTLBMissMQ));
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flopenrc #(2) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ});
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
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flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, CurrentPTE); // Capture page table entry from data cache
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assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
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flopenrc #(1)
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ITLBMissMReg(.clk(clk),
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.reset(reset),
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.en(StartWalk | EndWalk),
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.clear(EndWalk),
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.d(ITLBMissF),
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.q(ITLBMissFQ)); */
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
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assign AnyTLBMissM = DTLBMissM | ITLBMissF;
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assign StartWalk = WalkerState == IDLE & AnyTLBMissM;
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assign EndWalk = WalkerState == LEAF || WalkerState == FAULT;
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assign StartWalk = (WalkerState == IDLE) & AnyTLBMissM;
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assign EndWalk = (WalkerState == LEAF) || (WalkerState == FAULT);
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// unswizzle PTE bits
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assign {Dirty, Accessed, Global, User,
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@ -163,21 +150,75 @@ module pagetablewalker
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// Assign PTE descriptors common across all XLEN values
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assign LeafPTE = Executable | Writable | Readable;
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assign ValidPTE = Valid && ~(Writable && ~Readable);
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assign AccessAlert = ~Accessed | (MemStore & ~Dirty);
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assign ADPageFault = ~Accessed | (MemStore & ~Dirty);
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// Assign specific outputs to general outputs
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assign PageTableEntryF = PageTableEntry;
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assign PageTableEntryM = PageTableEntry;
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assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
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// *** is there a way to speed up HPTW?
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// TranslationPAdr mux
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if (`XLEN==32) begin
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logic [9:0] VPN1, VPN0;
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assign VPN1 = TranslationVAdr[31:22];
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assign VPN0 = TranslationVAdr[21:12];
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always_comb
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case (WalkerState)
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LEVEL1_SET_ADRE: TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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LEVEL1_WDV: TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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LEVEL1: if (NextWalkerState == LEAF) TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; // ***check this and similar
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else TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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LEVEL0_SET_ADRE: TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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LEVEL0_WDV: TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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LEVEL0: TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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LEAF: TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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default: TranslationPAdr = 0; // cause seg fault if this is improperly used
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endcase
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end else begin
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logic [8:0] VPN3, VPN2, VPN1, VPN0;
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assign VPN3 = TranslationVAdr[47:39];
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assign VPN2 = TranslationVAdr[38:30];
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assign VPN1 = TranslationVAdr[29:21];
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assign VPN0 = TranslationVAdr[20:12];
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always_comb
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case (WalkerState)
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LEVEL3_SET_ADRE: TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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LEVEL3_WDV: TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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LEVEL3: if (NextWalkerState == LEAF) TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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else TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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LEVEL2_SET_ADRE: TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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LEVEL2_WDV: TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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LEVEL2: if (NextWalkerState == LEAF) TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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else TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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LEVEL1_SET_ADRE: TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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LEVEL1_WDV: TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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LEVEL1: if (NextWalkerState == LEAF) TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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else TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
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LEVEL0_SET_ADRE: TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
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LEVEL0_WDV: TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
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LEVEL0: TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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LEAF: TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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default: TranslationPAdr = 0; // cause seg fault if this is improperly used
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endcase
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end
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// generate
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if (`XLEN == 32) begin
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logic [9:0] VPN1, VPN0;
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// *** make sure 32/34 bit addresses are being handled properly
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//logic [9:0] VPN1, VPN0;
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//assign VPN1 = TranslationVAdr[31:22];
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//assign VPN0 = TranslationVAdr[21:12];
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// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
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assign MegapageMisaligned = |(CurrentPPN[9:0]);
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// State transition logic
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always_comb begin
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PRegEn = 1'b0;
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TranslationPAdr = '0;
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HPTWRead = 1'b0;
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PageTableEntry = '0;
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PageType = '0;
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@ -188,60 +229,36 @@ module pagetablewalker
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WalkerLoadPageFaultM = 1'b0;
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WalkerStorePageFaultM = 1'b0;
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SelPTW = 1'b1;
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// SelPTW = 1'b1;
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case (WalkerState)
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IDLE: begin
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SelPTW = 1'b0;
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if (AnyTLBMissM & SvMode == `SV32) begin
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NextWalkerState = LEVEL1_SET_ADRE;
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end else begin
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NextWalkerState = IDLE;
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end
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end
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LEVEL1_SET_ADRE: begin
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NextWalkerState = LEVEL1_WDV;
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TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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end
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IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE;
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else NextWalkerState = IDLE;
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LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV;
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LEVEL1_WDV: begin
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TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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HPTWRead = 1'b1;
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if (HPTWStall) begin
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NextWalkerState = LEVEL1_WDV;
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end else begin
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if (HPTWStall) NextWalkerState = LEVEL1_WDV;
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else begin
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NextWalkerState = LEVEL1;
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PRegEn = 1'b1;
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end
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end
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LEVEL1: begin
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// *** <FUTURE WORK> According to the architecture, we should
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// fault upon finding a superpage that is misaligned or has 0
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// access bit. The following commented line of code is
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// supposed to perform that check. However, it is untested.
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if (ValidPTE && LeafPTE && ~BadMegapage) begin
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NextWalkerState = LEAF;
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TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) NextWalkerState = LEAF;
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else if (ValidPTE && ~LeafPTE) begin
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NextWalkerState = LEVEL0_SET_ADRE;
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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HPTWRead = 1'b1;
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end else begin
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NextWalkerState = FAULT;
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end
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NextWalkerState = LEVEL0_SET_ADRE;
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HPTWRead = 1'b1;
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end else NextWalkerState = FAULT;
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end
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LEVEL0_SET_ADRE: begin
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NextWalkerState = LEVEL0_WDV;
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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//TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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end
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LEVEL0_WDV: begin
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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//TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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HPTWRead = 1'b1;
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if (HPTWStall) begin
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NextWalkerState = LEVEL0_WDV;
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@ -252,9 +269,9 @@ module pagetablewalker
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end
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LEVEL0: begin
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if (ValidPTE & LeafPTE & ~AccessAlert) begin
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if (ValidPTE & LeafPTE & ~ADPageFault) begin
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NextWalkerState = LEAF;
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TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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//TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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end else begin
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NextWalkerState = FAULT;
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end
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@ -266,11 +283,11 @@ module pagetablewalker
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PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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//TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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end
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FAULT: begin
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SelPTW = 1'b0;
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//SelPTW = 1'b0;
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NextWalkerState = IDLE;
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WalkerInstrPageFaultF = ~DTLBMissMQ;
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WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
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@ -282,26 +299,9 @@ module pagetablewalker
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endcase
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end
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// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
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assign MegapageMisaligned = |(CurrentPPN[9:0]);
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assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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assign VPN1 = TranslationVAdr[31:22];
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assign VPN0 = TranslationVAdr[21:12];
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// Capture page table entry from data cache
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// *** may need to delay reading this value until the next clock cycle.
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// The clk to q latency of the SRAM in the data cache will be long.
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// I cannot see directly using this value. This is no different than
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// a load delay hazard. This will require rewriting the walker fsm.
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// also need a new signal to save. Should be a mealy output of the fsm
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// request followed by ~stall.
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flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE);
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//mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE);
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assign CurrentPTE = SavedPTE;
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assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
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// Assign outputs to ahblite
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// *** Currently truncate address to 32 bits. This must be changed if
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@ -310,13 +310,25 @@ module pagetablewalker
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end else begin
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logic [8:0] VPN3, VPN2, VPN1, VPN0;
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/* logic [8:0] VPN3, VPN2, VPN1, VPN0;
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assign VPN3 = TranslationVAdr[47:39];
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assign VPN2 = TranslationVAdr[38:30];
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assign VPN1 = TranslationVAdr[29:21];
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assign VPN0 = TranslationVAdr[20:12];*/
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logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
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logic TerapageMisaligned, GigapageMisaligned;
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// A terapage is a level 3 leaf page. This page must have zero PPN[2],
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// zero PPN[1], and zero PPN[0]
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assign TerapageMisaligned = |(CurrentPPN[26:0]);
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// A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and
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// zero PPN[0]
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assign GigapageMisaligned = |(CurrentPPN[17:0]);
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// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
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assign MegapageMisaligned = |(CurrentPPN[8:0]);
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always_comb begin
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PRegEn = 1'b0;
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TranslationPAdr = '0;
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//TranslationPAdr = '0;
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HPTWRead = 1'b0;
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PageTableEntry = '0;
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PageType = '0;
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@ -327,11 +339,9 @@ module pagetablewalker
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WalkerLoadPageFaultM = 1'b0;
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WalkerStorePageFaultM = 1'b0;
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SelPTW = 1'b1;
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case (WalkerState)
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IDLE: begin
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SelPTW = 1'b0;
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//SelPTW = 1'b0;
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if (AnyTLBMissM & SvMode == `SV48) begin
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NextWalkerState = LEVEL3_SET_ADRE;
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end else if (AnyTLBMissM & SvMode == `SV39) begin
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@ -343,11 +353,11 @@ module pagetablewalker
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LEVEL3_SET_ADRE: begin
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NextWalkerState = LEVEL3_WDV;
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TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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//TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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end
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LEVEL3_WDV: begin
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TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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//TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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HPTWRead = 1'b1;
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if (HPTWStall) begin
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NextWalkerState = LEVEL3_WDV;
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@ -358,18 +368,13 @@ module pagetablewalker
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end
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LEVEL3: begin
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// *** <FUTURE WORK> According to the architecture, we should
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// fault upon finding a superpage that is misaligned or has 0
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// access bit. The following commented line of code is
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// supposed to perform that check. However, it is untested.
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if (ValidPTE && LeafPTE && ~BadTerapage) begin
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if (ValidPTE && LeafPTE && ~(TerapageMisaligned || ADPageFault)) begin
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NextWalkerState = LEAF;
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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//TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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NextWalkerState = LEVEL2_SET_ADRE;
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TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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//TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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end else begin
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NextWalkerState = FAULT;
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end
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@ -377,11 +382,11 @@ module pagetablewalker
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LEVEL2_SET_ADRE: begin
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NextWalkerState = LEVEL2_WDV;
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TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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//TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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end
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LEVEL2_WDV: begin
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TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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//TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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HPTWRead = 1'b1;
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if (HPTWStall) begin
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NextWalkerState = LEVEL2_WDV;
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@ -396,14 +401,14 @@ module pagetablewalker
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// fault upon finding a superpage that is misaligned or has 0
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// access bit. The following commented line of code is
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// supposed to perform that check. However, it is untested.
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if (ValidPTE && LeafPTE && ~BadGigapage) begin
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if (ValidPTE && LeafPTE && ~(GigapageMisaligned || ADPageFault)) begin
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NextWalkerState = LEAF;
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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//TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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NextWalkerState = LEVEL1_SET_ADRE;
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TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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//TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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end else begin
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NextWalkerState = FAULT;
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end
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@ -411,11 +416,11 @@ module pagetablewalker
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LEVEL1_SET_ADRE: begin
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NextWalkerState = LEVEL1_WDV;
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TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
//TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
end
|
||||
|
||||
LEVEL1_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
//TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
HPTWRead = 1'b1;
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL1_WDV;
|
||||
@ -430,15 +435,15 @@ module pagetablewalker
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
if (ValidPTE && LeafPTE && ~BadMegapage) begin
|
||||
if (ValidPTE && LeafPTE && ~(MegapageMisaligned || ADPageFault)) begin
|
||||
NextWalkerState = LEAF;
|
||||
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
//TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL0_SET_ADRE;
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
//TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
@ -446,11 +451,11 @@ module pagetablewalker
|
||||
|
||||
LEVEL0_SET_ADRE: begin
|
||||
NextWalkerState = LEVEL0_WDV;
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
//TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
end
|
||||
|
||||
LEVEL0_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
//TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
HPTWRead = 1'b1;
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL0_WDV;
|
||||
@ -461,9 +466,9 @@ module pagetablewalker
|
||||
end
|
||||
|
||||
LEVEL0: begin
|
||||
if (ValidPTE && LeafPTE && ~AccessAlert) begin
|
||||
if (ValidPTE && LeafPTE && ~ADPageFault) begin
|
||||
NextWalkerState = LEAF;
|
||||
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
//TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
@ -476,12 +481,12 @@ module pagetablewalker
|
||||
((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
//TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
NextWalkerState = IDLE;
|
||||
end
|
||||
|
||||
FAULT: begin
|
||||
SelPTW = 1'b0;
|
||||
//SelPTW = 1'b0;
|
||||
NextWalkerState = IDLE;
|
||||
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
||||
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
||||
@ -496,30 +501,6 @@ module pagetablewalker
|
||||
endcase
|
||||
end
|
||||
|
||||
// A terapage is a level 3 leaf page. This page must have zero PPN[2],
|
||||
// zero PPN[1], and zero PPN[0]
|
||||
assign TerapageMisaligned = |(CurrentPPN[26:0]);
|
||||
// A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and
|
||||
// zero PPN[0]
|
||||
assign GigapageMisaligned = |(CurrentPPN[17:0]);
|
||||
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
|
||||
assign MegapageMisaligned = |(CurrentPPN[8:0]);
|
||||
|
||||
assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
|
||||
assign VPN3 = TranslationVAdr[47:39];
|
||||
assign VPN2 = TranslationVAdr[38:30];
|
||||
assign VPN1 = TranslationVAdr[29:21];
|
||||
assign VPN0 = TranslationVAdr[20:12];
|
||||
|
||||
|
||||
// Capture page table entry from ahblite
|
||||
flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE);
|
||||
//mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE);
|
||||
assign CurrentPTE = SavedPTE;
|
||||
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
||||
|
||||
// *** Major issue. We need the full virtual address here.
|
||||
// When the TLB's are update it use use the orignal address
|
||||
|
||||
Loading…
Reference in New Issue
Block a user