Rose Thompson
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89bf1a5cf9
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Fixed bug which broke the non Zicclsm configs.
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2023-11-10 16:08:04 -06:00 |
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Rose Thompson
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3e5aa77b5d
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Merge branch 'main' into Zicclsm
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2023-11-02 12:55:51 -05:00 |
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Rose Thompson
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7dafff27a5
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Enabled Zicclsm in rv64gc.
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2023-11-02 12:47:40 -05:00 |
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Rose Thompson
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92d4d7626c
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Merge pull request #449 from davidharrishmc/dev
Synthesis cleanup
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2023-11-02 12:26:55 -05:00 |
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Rose Thompson
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f89673d7e5
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Doesn't yet fully work.
Thomas is going to finish debugging while I'm on the RISCV summit next week.
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2023-11-02 12:07:42 -05:00 |
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David Harris
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c99d29cf95
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Removed .gitattributes
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2023-11-01 17:50:44 -07:00 |
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Rose Thompson
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3817d792f6
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Progress. I think the remaining bugs are in the regression test's signature.
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2023-11-01 17:51:48 -05:00 |
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Rose Thompson
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7b22b269f1
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Finally the d$ spill works. At least until the next bug. Definitely needs a lot of cleanup.
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2023-11-01 14:25:18 -05:00 |
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David Harris
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c639f92d27
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Improved comments about memory read paths
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2023-11-01 07:00:17 -07:00 |
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Rose Thompson
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b5ecae2056
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Working through issues with the psill logic.
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2023-10-31 18:50:13 -05:00 |
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Rose Thompson
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53bcb45844
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Progress
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2023-10-31 14:50:33 -05:00 |
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Rose Thompson
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0dd516e90f
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Fixed bugs in misaligned test.
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2023-10-31 12:49:35 -05:00 |
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Rose Thompson
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6223e8382d
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First stab at the misaligned test.
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2023-10-31 12:30:10 -05:00 |
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David Harris
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6f021aac54
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Fixes to config extraction
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2023-10-31 06:27:55 -07:00 |
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David Harris
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bd6e189680
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130 nm synthesis script improvements
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2023-10-30 20:57:35 -07:00 |
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David Harris
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d2ccba9a49
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Conditionally instantiate hardware in ifu
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2023-10-30 20:55:00 -07:00 |
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David Harris
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d0735887de
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Gated InstrOrigM and PCMReg when not needed
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2023-10-30 20:05:37 -07:00 |
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David Harris
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4bd830e578
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rom1p1r code cleanup
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2023-10-30 19:47:49 -07:00 |
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David Harris
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7b3dcdc262
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rom1p1r code cleanup
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2023-10-30 19:46:38 -07:00 |
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David Harris
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c472f4dc3c
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Made 2-bit AdrReg conditional on being needed
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2023-10-30 19:13:43 -07:00 |
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Rose Thompson
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7e8d132ead
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Updated mmu to not generate trap on cacheable misaligned access when supported.
Updated tests with David's help.
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2023-10-30 18:26:11 -05:00 |
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Rose Thompson
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2f5deff7bc
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Preemptively fixed the bytemask bug before testing.
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2023-10-30 15:47:46 -05:00 |
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Rose Thompson
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3824c3be8d
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rv32gc now also works with the alignment module. Still not tested with misligned access.
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2023-10-30 15:30:09 -05:00 |
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Rose Thompson
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f7b00c7af9
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Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests.
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2023-10-30 14:54:58 -05:00 |
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Rose Thompson
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560a843cea
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Finally lints cleanly.
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2023-10-30 14:00:49 -05:00 |
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Rose Thompson
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e3f769a563
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Merge pull request #445 from davidharrishmc/dev
Fix issue 444; no delegating misaligned instructions if they can't happen
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2023-10-30 12:25:42 -05:00 |
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David Harris
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4d191e63cc
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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David Harris
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12d1aed8a9
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Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.
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2023-10-30 07:06:34 -07:00 |
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Rose Thompson
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610969726e
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Progress.
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2023-10-27 16:31:22 -05:00 |
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Rose Thompson
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b2c61737bf
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Passes lint with some exceptions. Still need to add misaligned store support.
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2023-10-27 14:41:42 -05:00 |
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Rose Thompson
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42b2dad6ad
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At least have the aligner integrated, but not tested.
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2023-10-27 13:55:16 -05:00 |
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Rose Thompson
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ff85832454
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Addec ZICCLSM to config files and started on lsu instance.
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2023-10-27 13:07:23 -05:00 |
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Rose Thompson
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d648e199e1
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The misaligned load alignment lints.
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2023-10-27 11:41:49 -05:00 |
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Rose Thompson
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839ff28d32
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Added file.
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2023-10-27 09:49:44 -05:00 |
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Rose Thompson
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e7edd0084e
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Progress on misaligned load/stores.
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2023-10-27 09:35:44 -05:00 |
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Rose Thompson
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77e6ac487a
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Merge pull request #443 from davidharrishmc/dev
Wrapper synthesis fix.
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2023-10-27 09:25:06 -05:00 |
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David Harris
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5ca5443835
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Fixed reporting of timing on modules with wrappers
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2023-10-26 20:14:14 -07:00 |
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David Harris
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d5d196b870
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-10-26 19:02:05 -07:00 |
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David Harris
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b1796daca7
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Merge pull request #441 from ross144/main
Fixed issues #200
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2023-10-26 10:26:58 -07:00 |
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Rose Thompson
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9ca3bfc2c8
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Updated comments about Interrupt and wfi.
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2023-10-26 12:24:36 -05:00 |
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Rose Thompson
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63bcc7655c
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Forgot to include this file in the last commit.
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2023-10-26 12:20:42 -05:00 |
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Rose Thompson
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4c4103dfe8
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-10-26 12:15:22 -05:00 |
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Rose Thompson
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00851dab2a
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begin implemenation of Zicclsm.
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2023-10-26 11:51:20 -05:00 |
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Rose Thompson
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dd9059317f
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Cleaned up the implementation changes for wfi.
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2023-10-24 23:11:48 -05:00 |
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Rose Thompson
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e4aebbaaa5
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This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps.
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2023-10-24 22:58:26 -05:00 |
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Rose Thompson
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bc877e9ca7
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Possible fix for wfi.
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2023-10-24 18:08:33 -05:00 |
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David Harris
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17fd0c90da
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Fixed warnings of signed conversion and for Design Compiler
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2023-10-24 14:01:43 -07:00 |
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David Harris
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7fc5268f47
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Tested assembly language file for the pause example
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2023-10-24 10:45:41 -07:00 |
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David Harris
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de52710a60
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Merge pull request #439 from ross144/main
Fixes to branch predictor processing scripts.
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2023-10-24 08:31:06 -07:00 |
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Rose Thompson
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25a3a2f33b
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Fixed bug in bpred-sim.py for btb and class size sweep.
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2023-10-24 10:29:02 -05:00 |
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