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Author SHA1 Message Date
David Harris
381f3298d8 Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
David Harris
1ce0975366 Adjusting byte writes to RAM 2022-07-08 08:45:21 +00:00
David Harris
3f9e662201 Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
9b6d9666c5 Removed unused swbytemask from CLINT 2022-07-08 08:43:24 +00:00
Madeleine Masser-Frye
023b31a4d2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 08:02:19 +00:00
Madeleine Masser-Frye
8f0f626140 made wally synth flow shell based 2022-07-08 08:02:11 +00:00
Madeleine Masser-Frye
8e6aa12b2b restore flatten 2022-07-08 08:01:10 +00:00
David Harris
76ab5e7993 makefile 2022-07-07 16:43:03 -07:00
David Harris
10ebcd1f95 CoreMark makefile tuning 2022-07-07 16:42:30 -07:00
Katherine Parry
905b7ffc84 moved unsused division code again 2022-07-07 16:41:26 -07:00
cturek
b7e590ebb0 Sqrt exponents 2022-07-07 23:34:56 +00:00
Katherine Parry
5751d86f69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-07 16:29:44 -07:00
Katherine Parry
2bbde827e6 Revert "moved old divsqrt to unusedsrc" 
This reverts commit c9f5ae12ea.
 2022-07-07 16:29:17 -07:00
DTowersM
5a68ff9afb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-07 23:11:35 +00:00
DTowersM
d55833e4f3 new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory 2022-07-07 23:11:02 +00:00
Katherine Parry
c9f5ae12ea moved old divsqrt to unusedsrc 2022-07-07 16:09:56 -07:00
Katherine Parry
41c16be012 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
cturek
b41a6f069b Seventeen Square Root Tests 2022-07-07 22:48:46 +00:00
David Harris
96a75d7749 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 22:00:59 +00:00
Katherine Parry
08769e35ae modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
2f342c430e fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00
cturek
89e17b6f3c Preprocessing for square root 2022-07-07 21:23:30 +00:00
David Harris
88e3233935 Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
Madeleine Masser-Frye
3135e1202e plot tuning, fo4 axis 2022-07-07 16:44:02 +00:00
David Harris
7ab747dc43 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 15:57:50 +00:00
Madeleine Masser-Frye
528c24a02f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 15:52:05 +00:00
Madeleine Masser-Frye
2f28cbf909 updated synth flow to prevent runs from writing over each other's configs 2022-07-07 15:52:01 +00:00
David Harris
b7462ed6ed Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 15:51:33 +00:00
Madeleine Masser-Frye
8b92713cbd set input delay when flop-driven, added run clock 2022-07-07 15:50:34 +00:00
slmnemo
c5fd98ba99 sim-buildroot-batch now runs wally-pipelined-batch 
with option buildroot buildroot-no-trace to boot linux from step 0
 2022-07-06 18:06:43 -07:00
David Harris
6a030fc2a3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:44:47 +00:00
DTowersM
47a990d9f1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-06 23:44:27 +00:00
DTowersM
1e8ccf3449 added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu 2022-07-06 23:43:57 +00:00
David Harris
08ae2db080 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:43:05 +00:00
Ross Thompson
bd46cf76a9 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
cb33d2289b fixed width mismatch for rv64 ieuadrM and readdatawordM 2022-07-06 22:39:35 +00:00
David Harris
149301db32 Removed Sky130 libraries 2022-07-06 13:50:11 +00:00
David Harris
9ef38145d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 13:26:26 +00:00
David Harris
a599084b88 PLIC and UART passing tests on APB 2022-07-06 13:26:14 +00:00
slmnemo
f8059e9e40 Resolved conflicts between different gpio files 2022-07-05 18:38:52 -07:00
slmnemo
b3cd9de9e8 Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests. 2022-07-05 18:21:17 -07:00
Madeleine Masser-Frye
846f12aa2e new priority onehot module for better area/time 2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye
01e6d69a67 took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye
50e9b6ac53 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
Madeleine Masser-Frye
ca65ca2877 organized ppa files into ppa directory 2022-07-05 22:28:25 +00:00
cturek
e7ac99a683 Radix 2 Integer division working (without signs or remainder) 2022-07-05 21:34:49 +00:00
David Harris
d73645944f APB CLINT passing regression 2022-07-05 15:51:35 +00:00
David Harris
d033659beb Modified uncore to use AHB bridge to GPIO 2022-07-05 05:02:21 +00:00
David Harris
e7fe7ad0c8 AHB bridge for gpio 2022-07-05 05:01:59 +00:00