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2,561 Commits 4 Branches 2 Tags 53 MiB
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138 Commits

Author SHA1 Message Date
David Harris
87aa0724a2 IFU cleanup 2022-01-27 17:18:55 +00:00
David Harris
218ff3e25d IFU cleanup 2022-01-27 16:41:57 +00:00
David Harris
1c22077841 Optimized out second adder from IFU for PC+2 2022-01-27 16:06:24 +00:00
David Harris
62e5c7fd13 Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
Ross Thompson
9a9dfcae40 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-27 08:45:33 -06:00
Ross Thompson
d38ab9d2d7 Increased number of concurrent tests. 2022-01-27 08:45:25 -06:00
David Harris
975c0e72c8 Set up rv32emc config 2022-01-27 14:37:58 +00:00
Ross Thompson
75c33bc6c9 BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush. 2022-01-27 07:59:59 -06:00
Ross Thompson
b961b104e0 Added colors to regression script to make it easy to pick out success from fail. 2022-01-26 22:40:32 -06:00
Ross Thompson
c3a78553be Removed mux in PCNextF logic. Minor IFU improvements. 2022-01-26 22:33:26 -06:00
Ross Thompson
23c4ba2777 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
 2022-01-26 18:23:39 -06:00
Ross Thompson
2c982dca03 IFU simplifications. 2022-01-26 13:54:59 -06:00
David Harris
c6adb7b6b1 Updated configs to fix GPIO address to match FU540 2022-01-26 18:16:34 +00:00
David Harris
c60bb68bff Testgen working for Lab 2 2022-01-26 18:01:51 +00:00
Ross Thompson
728e46a794 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
David Harris
22c84dcd80 simpleram simplification 2022-01-25 19:46:13 +00:00
David Harris
8bf73d0eb3 simpleram simplification 2022-01-25 19:40:07 +00:00
David Harris
f07123ff0f simpleram simplification 2022-01-25 18:26:31 +00:00
David Harris
7ac44cb3fc simpleram address simplification 2022-01-25 18:17:33 +00:00
David Harris
5eb71a3bbe simpleram address simplification 2022-01-25 18:00:50 +00:00
David Harris
d9888c91a6 simpleram clk and reset simplification 2022-01-25 17:34:15 +00:00
David Harris
5cb879129e Start of IFU cleanup 2022-01-25 17:31:53 +00:00
Ross Thompson
4d4d9ac8cf Added spill support back into the IROM IFU. 2022-01-21 15:50:54 -06:00
Ross Thompson
4ecc2d029a Changed the IROM and DTIM memories to behave like edge-triggered srams. 2022-01-21 15:42:54 -06:00
David Harris
c2c7351b24 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-21 00:12:18 +00:00
David Harris
0bb63e9ad1 Fixed path to riscvOVPsimPlus 2022-01-21 00:12:14 +00:00
Ross Thompson
ec44774c77 Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv 2022-01-20 16:39:54 -06:00
David Harris
ca1f7ce5d3 Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
David Harris
0d0aa59e48 Removed imperas tests from makefile for now 2022-01-20 14:51:56 +00:00
David Harris
f420e63ed0 Added top-level make clean 2022-01-20 14:17:26 +00:00
David Harris
537cb1d1e1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-20 00:04:27 +00:00
Ross Thompson
05ebadacad Added PCNextF and PostSpillInstrRawF to ila. 2022-01-19 14:05:14 -06:00
David Harris
f966d98e56 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-19 00:26:34 +00:00
Ross Thompson
5cf686429d Merged in the debug ila updates. 2022-01-18 17:29:21 -06:00
Ross Thompson
2508b9d35a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-18 17:19:59 -06:00
Ross Thompson
fdc17f5017 Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes. 2022-01-18 17:19:33 -06:00
David Harris
1a21e7f011 riscvsingle reparittioned to match Ch4 2022-01-17 16:57:32 +00:00
David Harris
de7b9c127e Added E extension, and downloaded riscv-dv and embench-iot to addins 2022-01-17 14:42:59 +00:00
David Harris
5842d780a7 Defined rv32e and rv32emc configs 2022-01-17 14:01:01 +00:00
David Harris
8b62130070 lsu cleanup down to 346 lines 2022-01-15 01:19:44 +00:00
David Harris
b967bcede2 LSU Cleanup 2022-01-15 01:11:17 +00:00
David Harris
f7f3882cb8 Moved Dcache into bus block 2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe Renamed LSUStall to LSUStallM 2022-01-15 00:24:16 +00:00
David Harris
b0263012e8 LSU cleanup 2022-01-15 00:11:30 +00:00
David Harris
4c5962095e LSU cleanup 2022-01-15 00:03:03 +00:00
David Harris
37bf5347cf LSU cleanup 2022-01-14 23:55:27 +00:00
Ross Thompson
dd1ebb75f0 Fixed spillthreshold warning. 2022-01-14 17:23:39 -06:00
Ross Thompson
9d2a79f180 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-14 17:16:53 -06:00
David Harris
380e990def moved fp to tests 2022-01-14 23:05:59 +00:00
David Harris
291deb5c39 LSU partitioning 2022-01-14 23:02:28 +00:00