David Harris
861fbd698b
Run 4M instructions in buildroot test to get through kernel & VirtMem startup
2022-04-18 01:29:38 +00:00
David Harris
2819a1c305
Remvoed bytemask anding from FinalWriteDataM in subwordwrite
2022-04-17 22:33:25 +00:00
David Harris
812b56acc6
Prefix comparator cleanup
2022-04-17 21:53:11 +00:00
David Harris
de5b61291f
Experiments with prefix comparator; minor fixes in WFI and testbench warnings
2022-04-17 21:43:12 +00:00
Kip Macsai-Goren
7a99066427
removed broken test from makefrag
2022-04-17 21:25:56 +00:00
Kip Macsai-Goren
1f9c987efe
added new tests to makefrag and tests.vh
2022-04-17 21:00:36 +00:00
Kip Macsai-Goren
62ac6f0dbe
added more comprehensive vectoring, interrupt causing and handing
2022-04-17 20:57:12 +00:00
Kip Macsai-Goren
7ea77d1038
Added the rest of the tests lited in Chapter 5 test plan
2022-04-17 20:57:12 +00:00
Ross Thompson
059c04e2a8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-17 15:23:46 -05:00
Ross Thompson
c16dec88de
Increased uart baud rate to 230400.
...
Added uart signals to debugger.
2022-04-17 15:23:39 -05:00
David Harris
2436534687
First implementation of WFI timeout wait
2022-04-17 17:20:35 +00:00
David Harris
83d283354c
Added comments in fcvt
2022-04-17 16:53:10 +00:00
David Harris
aa1bac361d
Simplified SLT logic
2022-04-17 16:49:51 +00:00
Ross Thompson
238cc9f9fd
Commented output power analysis to speed simulation.
2022-04-16 15:32:59 -05:00
Ross Thompson
4d3fde3829
Updated wally to point to riscv-arch-test tag 2.7.3
2022-04-16 15:32:43 -05:00
Ross Thompson
57358c884e
commented out wally-scratch test as it hangs during compile.
2022-04-16 15:09:17 -05:00
Ross Thompson
16b3c64234
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-16 14:59:03 -05:00
Ross Thompson
b9a19304db
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
James E. Stine
600a2c5e2f
Update mkdir in run_all.sh to guarantee no errors
2022-04-14 22:23:23 -05:00
David Harris
68d9c99fba
Added WFI support to IFU to keep it in the pipeline
2022-04-14 17:26:17 +00:00
David Harris
a28831b83e
Added WFI to the testbench instruction name decoder
2022-04-14 17:12:11 +00:00
David Harris
855d68afde
WFI should set EPC to PC+4
2022-04-14 17:05:22 +00:00
bbracker
fe53dd1683
fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM
2022-04-14 09:23:21 -07:00
bbracker
eb21e34000
fix ReadDataM forcing
2022-04-13 15:32:00 -07:00
bbracker
3aec080e15
parsePlicState.py bugfix
2022-04-13 13:04:43 -07:00
Ross Thompson
2e8afd071e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-13 13:39:47 -05:00
bbracker
5de92af0b1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-13 05:35:56 -07:00
bbracker
735c75af55
change interrupt spoofing to happen at negative clock edges
2022-04-13 04:31:23 -07:00
bbracker
52ed99ca1b
improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
2022-04-13 03:37:53 -07:00
bbracker
6c56f52e7c
fix bugs in PLIC checkpoint state parsing
2022-04-13 01:59:21 -07:00
bbracker
777de6e05b
whoops fix address for PLIC int enables in checkpoint generation
2022-04-13 01:36:09 -07:00
bbracker
03f1c01f14
whoops forgot to update AttemptedInstructionCount in interrupt spoofing
2022-04-13 00:49:37 -07:00
bbracker
d3e9703c19
change testbench-linux to by default use attempted instruction count for warning/error messages
2022-04-12 21:22:08 -07:00
Ross Thompson
bb6f1cf816
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-12 19:38:04 -05:00
Ross Thompson
fc173a7954
Missed the force on uart for no tracking.
2022-04-12 19:37:44 -05:00
Ross Thompson
ff826fdb02
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-12 17:56:48 -05:00
Ross Thompson
7d0462dc59
UART and clock speed changes to support 30Mhz.
2022-04-12 17:56:36 -05:00
Ross Thompson
ab9738d3be
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
02d6829f8e
Found the complex TrapM giving back the wrong instruction bug.
...
As I was reviewing the busfsm I found a typo.
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
It should be
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.
2022-04-11 13:07:52 -05:00
Ross Thompson
f995ec2a54
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-10 13:41:27 -05:00
Ross Thompson
c3d9eafe60
Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
2022-04-10 13:27:54 -05:00
bbracker
aa71fe542d
upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs
2022-04-08 13:45:27 -07:00
bbracker
3b6cb5f0ba
small signs of life on new interrupt spoofing
2022-04-08 12:32:30 -07:00
bbracker
9cee21ea35
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-07 19:43:27 -07:00
bbracker
3c1deb551d
deprecate remove_dup.awk in favor of expanding parseGDBtoTrace.py to internally remove duplicates; this way the instruction counts in traps.txt are hopefully now in sync with the line numbers of all.txt
2022-04-07 19:43:22 -07:00
Ross Thompson
43a294dc88
Added signals to ila.
2022-04-07 21:09:50 -05:00
Ross Thompson
8315d1816f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-07 16:56:56 -05:00
Ross Thompson
2294cbc1c6
Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.
2022-04-07 16:56:28 -05:00
Ross Thompson
8c2382be45
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-07 16:29:48 -05:00
Ross Thompson
9db8471bf2
Added sp to ila.
2022-04-07 16:29:41 -05:00
