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Author SHA1 Message Date
Alec Vercruysse
857956ac1e Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign 
FlushWay is always 1 for one way, but by default it is only 1 for
way 0.

The logic that advances FlushWay to ways 1, 2, and 3 only does so
on a subset of conditions that SelFlush is high (in cachefsm), so
this is unreachable for cachways 1-3.
 2023-04-25 17:02:53 -07:00
Alec Vercruysse
c19ed1990f extend invalidatecache d$ exclusion to statement coverage 2023-04-25 17:00:13 -07:00
David Harris
e73922d34d Merge pull request #275 from dherreravicioso/main 
Excluded coverage for impossible cases in wficountreg and status.MPRV
 2023-04-24 12:18:55 -07:00
Diego Herrera Vicioso
d29dc30288 Excluded coverage for impossible cases in wficountreg and status.MPRV 2023-04-24 02:06:53 -07:00
Ross Thompson
a353bbc3f1 Merge pull request #272 from davidharrishmc/dev 
fdivsqrt coverage and fix bug of not trapping on access to odd-numbered pmpcfg
 2023-04-23 12:22:14 -05:00
David Harris
52f49ed24d Fault on writes to odd-numbered PMPCFG in RV64 2023-04-22 15:32:39 -07:00
David Harris
3b299fb77a Removed unproven fdivsqrt exclusion 2023-04-22 15:27:05 -07:00
David Harris
086556310c Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage. 2023-04-22 12:22:45 -07:00
David Harris
063e41806e Fixted syntax error in exclusion. Arbitrarily picked -e 1; fix if this isn't right 2023-04-22 10:07:48 -07:00
David Harris
69cc0b8bf3 test plan update 2023-04-22 09:38:14 -07:00
David Harris
a8acd60d71 Merge pull request #270 from liamchalk00/main 
pmpcfg test cases
 2023-04-22 08:41:11 -07:00
Liam
c2f441724b pmpcfg test cases 
Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
 2023-04-21 20:43:37 -07:00
Ross Thompson
89065009ef Merge pull request #266 from davidharrishmc/dev 
FDivSqrt cleanup
 2023-04-21 20:23:23 -05:00
David Harris
8a59a4ce94 fdivsqrt cleanup 2023-04-20 17:35:01 -07:00
David Harris
86107e6136 continued cleanup 2023-04-20 16:48:23 -07:00
David Harris
33c0f64457 Reordered fdivsqrtpreproc to follow logic 2023-04-20 16:38:47 -07:00
David Harris
2c47268f50 Started fdivsqrtpreproc flow organization 2023-04-20 16:25:19 -07:00
David Harris
f2ae770e17 Fmv h/q comments in controller 2023-04-20 16:24:58 -07:00
David Harris
9f90c9efeb Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-20 16:07:37 -07:00
David Harris
b9d641f13a Merge pull request #256 from cturek/main 
Simplifying fds to follow diagram
 2023-04-20 16:07:22 -07:00
David Harris
d772806000 Merge pull request #265 from Noah-G-L/main 
Add Coverage for TLB, MP, Global, ASID and Match
 2023-04-20 16:06:09 -07:00
Noah Limpert
a0e71c26cb Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126 Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
David Harris
2bd8b65a2b Update README.md 2023-04-20 14:15:34 -07:00
David Harris
65c04489f1 Update README.md 2023-04-20 14:09:32 -07:00
Ross Thompson
faac8d439a Merge pull request #264 from davidharrishmc/dev 
Added -fp flag to run arch64d/f tests in coverage
 2023-04-20 09:26:16 -05:00
David Harris
9539306026 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-19 14:50:09 -07:00
David Harris
3a8d2db194 Merge pull request #262 from SydRiley/main 
removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
 2023-04-19 14:49:50 -07:00
Sydeny
ec730a7230 clarifying comments in exclusions 2023-04-19 14:47:34 -07:00
Sydeny
a132ffa7f7 removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98% 2023-04-19 13:30:12 -07:00
David Harris
ea9639435e Added -fp flag to run arch64d/f tests in coverage 2023-04-19 13:07:07 -07:00
David Harris
dad4331cb9 Merge pull request #261 from liamchalk00/main 
Add pmpcfg test cases increasing IFU coverage
 2023-04-19 12:37:19 -07:00
Liam
4f57dca0dc Add pmpcfg test cases increasing IFU coverage 2023-04-19 11:58:22 -07:00
David Harris
6e612a1693 Update tests.vh 
Missing comma from merge
 2023-04-19 06:23:05 -07:00
David Harris
3d9ae82dec Merge pull request #259 from AlecVercruysse/coverage4 
D$ Coverage
 2023-04-19 06:17:01 -07:00
David Harris
4cbffd7972 Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
6081fcbb45 Merge pull request #258 from liamchalk00/main 
Add test cases for pmpcfg.S
 2023-04-19 04:52:59 -07:00
David Harris
b63dff098a Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
David Harris
7d3bc6171c Merge pull request #257 from koooo142857/main 
PMPCFG_ARRAY_REGW cases
 2023-04-19 04:47:12 -07:00
David Harris
156a098884 Merge branch 'main' into main 2023-04-19 04:46:51 -07:00
David Harris
acde82b23e Merge pull request #255 from kjprime/main 
Add PR#252 test file to coverage
 2023-04-19 04:43:25 -07:00
Alec Vercruysse
faaf266558 CacheFSM logic simplification for AMO operations 
Ran this by Ross.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
de93bd6937 D$ scope-specific coverage exclusions (I$ logic that never fires) 
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
b3a3af8ed3 add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
9ef85c547b fix unhit exclusion in fdivsqrtfsm 2023-04-19 01:34:01 -07:00
Liam
9b72d6ac37 Update tests.vh 2023-04-18 23:15:47 -07:00
Liam
d74768ce04 Add test cases for pmpcfg.S 2023-04-18 23:06:52 -07:00
Kevin Wan
b5a3ff2d2d a 2023-04-18 22:09:50 -07:00
Kevin Wan
c91784bd5a Merge branch 'main' of https://github.com/koooo142857/cvw into main 2023-04-18 21:55:06 -07:00