cturek
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83051a5351
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Changed lzc names, started int/fp size merge in preproc
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2022-11-06 22:21:35 +00:00 |
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cturek
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2cbe2fd70b
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Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
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2022-11-06 22:08:18 +00:00 |
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cturek
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6bc4c1318e
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Added new macros for int div preprocessing, added p, n, and rightshiftx logic
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2022-11-06 21:53:48 +00:00 |
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Kip Macsai-Goren
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90ef371abc
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fixed fifo timout handling. error now in data ready interrupt
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2022-11-05 13:34:24 -07:00 |
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David Harris
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53a88fec8f
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Reorder embench tests to prevent crash
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2022-11-04 15:21:51 -07:00 |
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David Harris
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60cfa0d69c
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HPTW cleanup
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2022-11-04 15:21:09 -07:00 |
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Kip Macsai-Goren
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c06da6e6fe
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fixed broken instructions so make works.
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2022-11-03 23:06:20 +00:00 |
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Ross Thompson
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65feca8bed
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-03 17:48:35 -05:00 |
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Ross Thompson
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f1eb20ef4d
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Updated to put dtb into the rodata segment for our linker script.
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2022-11-03 17:48:20 -05:00 |
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cturek
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06a9305766
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renamed remOp to RemOp
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2022-11-03 22:37:25 +00:00 |
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Ross Thompson
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1d7002e5c5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-03 17:36:04 -05:00 |
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Ross Thompson
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ccce0df535
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Potentially a valid zero stage boot loader based on cva6.
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2022-11-03 17:35:57 -05:00 |
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cturek
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e37f564e84
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Added rem/div operation to postprocessor
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2022-11-02 17:49:40 +00:00 |
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cturek
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e8d7607e87
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Added buffered signals for int/fp
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2022-10-28 21:47:24 +00:00 |
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Ross Thompson
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103514a8e0
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More outline for uart timeout interrupt.
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2022-10-28 13:53:56 -05:00 |
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Ross Thompson
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21eca47d2e
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Untested change to uart test for outline of how to handle rx fifo timeout.
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2022-10-28 13:31:16 -05:00 |
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cturek
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9f41e57f03
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Config Cleanup
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2022-10-27 22:38:56 +00:00 |
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Ross Thompson
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dc3a9f2342
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-26 14:48:50 -05:00 |
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Ross Thompson
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403434580d
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Fixed the uart transmit fifo overrun bug.
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2022-10-26 14:48:09 -05:00 |
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cturek
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7301fc7f18
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small signal cleanup
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2022-10-26 18:42:49 +00:00 |
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cturek
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6caf7bb7e2
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abs for int inputs
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2022-10-26 16:18:05 +00:00 |
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cturek
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ec4646b412
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Added signed division to fdivsqrt
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2022-10-26 16:13:41 +00:00 |
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cturek
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71d16eacef
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unbroke DIVb
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2022-10-26 16:11:51 +00:00 |
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cturek
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1febdb75b7
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Config cleanup
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2022-10-25 21:04:09 +00:00 |
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Jacob Pease
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160ca366c8
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Added PLIC signals for debugging on FPGA.
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2022-10-25 13:57:09 -05:00 |
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cturek
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ff7d6b2932
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Started Integer Preprocessing
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2022-10-25 17:48:43 +00:00 |
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Kip Macsai-Goren
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6e45698b86
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Added test for UART FIFO timeout. Does not pass regression
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2022-10-25 05:35:56 +00:00 |
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Kip Macsai-Goren
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7448ee5e84
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added additional cache stats to coremark postprocess script
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2022-10-25 02:56:25 +00:00 |
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Kip Macsai-Goren
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5eb331b65e
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added I cache stats to coremark output
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2022-10-25 02:55:32 +00:00 |
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Ross Thompson
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d58a862f59
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Added new device trees for vcu118 and vcu108 boards.
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2022-10-24 17:45:10 -05:00 |
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Ross Thompson
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9ba487c323
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Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
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2022-10-24 15:38:39 -05:00 |
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Ross Thompson
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92ace4d8f7
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Forget to include updated xdc file.
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2022-10-24 13:51:21 -05:00 |
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Ross Thompson
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7244ca1e7b
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Bit width error.
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2022-10-24 13:48:47 -05:00 |
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Ross Thompson
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048ed01554
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-24 10:12:39 -05:00 |
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Ross Thompson
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51408c620e
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Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
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2022-10-23 13:46:50 -05:00 |
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Ross Thompson
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775309165b
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Small cleanup of interlockfsm.
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2022-10-22 16:29:51 -05:00 |
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Ross Thompson
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a59df0c77d
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Created one off test to replicate the floating point forwarding hazard bug.
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2022-10-22 16:29:12 -05:00 |
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Ross Thompson
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6696624971
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comment updates.
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2022-10-22 16:28:44 -05:00 |
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Ross Thompson
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12c5525807
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-22 16:27:30 -05:00 |
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Ross Thompson
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4db912678d
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Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.
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2022-10-22 16:27:20 -05:00 |
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Jacob Pease
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b1170ec7a2
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Extended rxfifotimeout count to actually be 4 characters long.
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2022-10-20 17:35:49 -05:00 |
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Ross Thompson
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897982400c
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Updated the device tree to use 30Mhz instead of 10Mhz for the cpu timebase.
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2022-10-20 15:05:39 -05:00 |
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Ross Thompson
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a008c61939
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Updated debug2.xdc for interlock fsm changes.
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2022-10-19 17:34:47 -05:00 |
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Ross Thompson
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2c5847b01f
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Moving interlockfsm changes to a temporary branch.
reduced complexity of cache mux controls.
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2022-10-19 15:08:23 -05:00 |
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Ross Thompson
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9cadd4c6ec
|
Broken don't use this state.
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2022-10-19 14:31:22 -05:00 |
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Ross Thompson
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c6a9b17918
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Noted possible bug with endianness during hptw.
Minor complexity reduction in interlockfsm. I think there is a lot of room to simplify.
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2022-10-19 12:20:19 -05:00 |
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Ross Thompson
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a53ca5c99f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-19 10:42:31 -05:00 |
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Ross Thompson
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d6f907f444
|
Sort of solved the bit width warning for dtim, irom ranges.
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2022-10-19 10:42:19 -05:00 |
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Ross Thompson
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d4c5440f25
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-18 15:06:09 -05:00 |
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Ross Thompson
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92accfb1a6
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Updated uart settings and fpga wave config.
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2022-10-18 15:05:33 -05:00 |
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