Kip Macsai-Goren
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32923cb250
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-05-25 15:28:19 -04:00 |
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Ross Thompson
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735e511073
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fixed bug with icache miss spill fsm branch.
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2021-05-25 14:26:22 -05:00 |
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James E. Stine
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e32e812f6a
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Update FPregfile to use more compact code and better structure for ease in reading
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2021-05-25 13:21:59 -05:00 |
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Ross Thompson
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aa9a81b760
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Merge remote-tracking branch 'refs/remotes/origin/main' into main
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2021-05-24 23:25:36 -05:00 |
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Ross Thompson
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13034c7406
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Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.
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2021-05-24 23:24:54 -05:00 |
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Kip Macsai-Goren
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ba134eb166
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partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
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2021-05-24 20:59:26 -04:00 |
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James E. Stine
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bbc1dfb309
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Minor cosmetic elements on div.sv
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2021-05-24 19:30:28 -05:00 |
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James E. Stine
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1704fdc877
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Mod for DIV/REM instruction and update to div.sv unit
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2021-05-24 19:29:13 -05:00 |
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bbracker
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82a6ee4c0e
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slightly more path independence for using verilator
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2021-05-24 18:11:56 -04:00 |
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bbracker
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d7405e476e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-05-24 17:09:14 -04:00 |
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bbracker
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7e2073e482
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peripheral testing standardization
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2021-05-24 17:08:40 -04:00 |
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Ross Thompson
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3c5e87d6c2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-05-24 14:28:41 -05:00 |
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Katherine Parry
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03aea055fa
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FMV.X.D imperas test passes
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2021-05-24 14:44:30 -04:00 |
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Ross Thompson
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dd26b754eb
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Fixed minor bug in instruction class decoding.
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2021-05-24 13:41:14 -05:00 |
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Ross Thompson
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b06fda88ff
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Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).
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2021-05-24 12:37:16 -05:00 |
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Ross Thompson
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daf344f1ba
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Updated branch predictor tests/benchmarks.
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2021-05-24 11:13:33 -05:00 |
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James E. Stine
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194c32defa
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Update header for FPadd
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2021-05-24 08:28:16 -05:00 |
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Katherine Parry
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55f22979ca
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FSD and FLD imperas tests pass
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2021-05-23 18:33:14 -04:00 |
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bbracker
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142b02b30a
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improved PLIC test organization
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2021-05-21 15:13:02 -04:00 |
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James E. Stine
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49a4097d97
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Minor testbench updates to rv64icfd
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2021-05-21 09:41:21 -05:00 |
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James E. Stine
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47487a625f
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Update to testbench-imperase for rv64icfd
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2021-05-21 09:28:44 -05:00 |
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James E. Stine
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694e21541b
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Update to FLD/FSD testbench
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2021-05-21 09:26:55 -05:00 |
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James E. Stine
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474d479280
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Update to rv64icfd wally-config to run through FP tests
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2021-05-21 09:22:17 -05:00 |
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Katherine Parry
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67a41748ba
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FMV.D.X imperas test passes
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2021-05-20 22:18:33 -04:00 |
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Katherine Parry
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71e4a10efb
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FMV.D.X imperas test passes
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2021-05-20 22:17:59 -04:00 |
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bbracker
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114bba8370
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small bit of busybear debug progress
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2021-05-19 20:18:00 -04:00 |
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bbracker
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8554f2f3cd
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plic implementation optimizations
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2021-05-19 18:10:48 +00:00 |
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bbracker
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fd4fae0406
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commented out MSTATUS test
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2021-05-19 12:38:01 -04:00 |
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James E. Stine
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058b265d18
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Update rv64icfd batch script
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2021-05-18 16:01:53 -05:00 |
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James E. Stine
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f407bee5ae
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Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
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2021-05-18 13:48:44 -05:00 |
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bbracker
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18ab9015f9
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-05-18 14:33:40 -04:00 |
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bbracker
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f43ea946aa
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changed lint script to use absolute path for verilator because cron jobs stink at using paths
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2021-05-18 14:33:22 -04:00 |
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David Harris
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7dcc53dcf5
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fixed rv64mmu makefile
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2021-05-18 14:25:55 -04:00 |
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David Harris
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5f214d60b6
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Removed rv64wally
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2021-05-18 14:08:46 -04:00 |
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David Harris
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433ea61d9e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/regression/vish_stacktrace.vstf
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2021-05-18 14:01:19 -04:00 |
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bbracker
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9b3332f3c3
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commented changes to imperas makefiles
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2021-05-18 13:34:48 -04:00 |
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Katherine Parry
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409438bc95
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floating point infinite loop removed from imperas tests
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2021-05-18 10:42:51 -04:00 |
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bbracker
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c08f5e6732
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script for running make and logging output
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2021-05-17 22:12:18 -04:00 |
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bbracker
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31c29b0cf1
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changed makefiles so that make stops at bad source code that does not compile
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2021-05-17 21:20:30 -04:00 |
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bbracker
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86d55cd07a
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fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
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2021-05-17 19:25:54 -04:00 |
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bbracker
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69ef758e78
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regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
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2021-05-17 18:44:47 -04:00 |
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David Harris
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1aa1908994
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Deleted vish_stacktrace
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2021-05-17 18:39:01 -04:00 |
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David Harris
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42483e5e03
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Started MSTATUS tests
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2021-05-17 18:37:56 -04:00 |
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James E. Stine
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49cc330bd9
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Forgot initialization config for div - apologies
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2021-05-17 17:12:27 -05:00 |
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Elizabeth Hedenberg
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853c9243c1
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commit ehedenberg coremark
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2021-05-17 18:02:35 -04:00 |
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Elizabeth Hedenberg
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9d17950c1d
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coremark commit ehedenberg final
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2021-05-17 18:02:34 -04:00 |
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James E. Stine
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96eca3287f
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Add 32/64-bit shifter for update to shifter block
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2021-05-17 17:02:13 -05:00 |
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James E. Stine
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8822bdd6ad
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Cleanup of regression
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2021-05-17 16:58:15 -05:00 |
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James E. Stine
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41da78e0b6
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Mod Imperas Testbench for updated Div/Rem
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2021-05-17 16:56:30 -05:00 |
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James E. Stine
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97cbdae674
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Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
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2021-05-17 16:48:51 -05:00 |
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