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Author SHA1 Message Date
Rose Thompson
7e8d132ead Updated mmu to not generate trap on cacheable misaligned access when supported. 
Updated tests with David's help.
 2023-10-30 18:26:11 -05:00
Rose Thompson
2f5deff7bc Preemptively fixed the bytemask bug before testing. 2023-10-30 15:47:46 -05:00
Rose Thompson
3824c3be8d rv32gc now also works with the alignment module. Still not tested with misligned access. 2023-10-30 15:30:09 -05:00
Rose Thompson
f7b00c7af9 Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests. 2023-10-30 14:54:58 -05:00
Rose Thompson
560a843cea Finally lints cleanly. 2023-10-30 14:00:49 -05:00
Rose Thompson
610969726e Progress. 2023-10-27 16:31:22 -05:00
Rose Thompson
b2c61737bf Passes lint with some exceptions. Still need to add misaligned store support. 2023-10-27 14:41:42 -05:00
Rose Thompson
42b2dad6ad At least have the aligner integrated, but not tested. 2023-10-27 13:55:16 -05:00
Rose Thompson
ff85832454 Addec ZICCLSM to config files and started on lsu instance. 2023-10-27 13:07:23 -05:00
Rose Thompson
d648e199e1 The misaligned load alignment lints. 2023-10-27 11:41:49 -05:00
Rose Thompson
839ff28d32 Added file. 2023-10-27 09:49:44 -05:00
Rose Thompson
e7edd0084e Progress on misaligned load/stores. 2023-10-27 09:35:44 -05:00
Rose Thompson
00851dab2a begin implemenation of Zicclsm. 2023-10-26 11:51:20 -05:00
Rose Thompson
dd9059317f Cleaned up the implementation changes for wfi. 2023-10-24 23:11:48 -05:00
Rose Thompson
e4aebbaaa5 This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps. 2023-10-24 22:58:26 -05:00
Rose Thompson
bc877e9ca7 Possible fix for wfi. 2023-10-24 18:08:33 -05:00
Rose Thompson
25a3a2f33b Fixed bug in bpred-sim.py for btb and class size sweep. 2023-10-24 10:29:02 -05:00
Rose Thompson
bad9afc012 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-23 16:14:30 -05:00
Rose Thompson
c296bd3a02 Updated bpred-sim.py to take command line options to select between sweeping direction, target, class, or ras prediction. 2023-10-23 16:09:40 -05:00
Rose Thompson
bce15ce367 Added support for branch counters when there is no branch predictor. 2023-10-23 15:32:03 -05:00
Rose Thompson
2b031ea445 Fixed issue 250. instruction classification was not correct for jalr ra (non zero). 2023-10-23 15:30:43 -05:00
Rose Thompson
7347ed2527 Addeed script to sweep sim_bp for btb. 2023-10-23 15:29:50 -05:00
David Harris
deebc84084
Merge pull request #438 from ross144/main 
Fixed comments in cboz and cbom tests.
 2023-10-20 17:15:59 -07:00
Rose Thompson
e3154bb7a3 Updated comments in the cboz tests. 2023-10-20 15:15:47 -05:00
Rose Thompson
74574f96cf Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-20 15:14:02 -05:00
Rose Thompson
badfc1e4bb Updated comments for the cbom tests. 2023-10-20 15:13:52 -05:00
Rose Thompson
99671ebbcd
Merge pull request #437 from davidharrishmc/dev 
synth improvements
 2023-10-19 16:23:34 -05:00
David Harris
46d16305a4 Set drive for Sky130 2023-10-19 13:46:30 -07:00
David Harris
aa3bc10259 Modified log2 coding to avoid synthesis warning 2023-10-19 11:16:02 -07:00
Rose Thompson
c5de241436
Merge pull request #436 from davidharrishmc/dev 
Automatic generation of synthesis wrappers when needed
 2023-10-19 12:51:24 -05:00
David Harris
b28777fae0 Removed wrapper from wallySynth because it is automatic now 2023-10-19 10:49:06 -07:00
David Harris
8c6b17de6d Updated wrapper generation to be automatic without specifying WRAPPER=1; instead looks for cvw_t in the file. Also starting to add OSU 130 nm synthesis. 2023-10-19 10:44:03 -07:00
David Harris
379337fee0 Adjusted synthesis scripts to report on DESIGN even when a wrapper is used 2023-10-19 06:16:52 -07:00
Rose Thompson
ba6785d04f
Merge pull request #434 from davidharrishmc/dev 
Config and peripheral cleanup
 2023-10-18 17:58:29 -05:00
David Harris
054d9ed38c Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-18 14:40:19 -07:00
David Harris
46b1ff00d6
Merge pull request #435 from kipmacsaigoren/synth_wrapper_gen 
synth wrapper generation bug fix
 2023-10-18 14:34:37 -07:00
Kevin Kim
0a15466f21 wrapper bug fix 2023-10-18 14:29:46 -07:00
David Harris
09b3a49471 Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates 2023-10-18 05:50:41 -07:00
David Harris
b01e1604e0 Config file cleanup 2023-10-18 05:38:36 -07:00
David Harris
f663b26e14
Merge pull request #433 from ross144/main 
Reverted linux testbench to not check for match against QEMU.
 2023-10-17 11:13:11 -07:00
Rose Thompson
b3a248cc5b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-17 10:01:35 -05:00
Rose Thompson
55c1560467 Reverted linux testbench to not check for match against QEMU. 2023-10-17 10:00:50 -05:00
Rose Thompson
dd7f7b5c6e
Merge pull request #431 from davidharrishmc/dev 
Dev
 2023-10-16 17:36:31 -05:00
David Harris
8dd1617409 Merged testbench 2023-10-16 13:52:24 -07:00
David Harris
b39ba7b4f8 Renamed wally-config to config in many comments 2023-10-16 13:49:09 -07:00
David Harris
1e2f1089ca Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
David Harris
5f9b555b93 Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc. 2023-10-15 15:31:03 -07:00
David Harris
88745f9265 Added WALLY minfo test for rv32 2023-10-15 06:48:22 -07:00
David Harris
b8a17afd5d minfo test working again with mconfigptr for RV64 2023-10-15 06:41:52 -07:00
David Harris
cc14c0a858
Merge pull request #429 from ross144/main 
renamed imperas testbench to testbench-imperas.sv, fixed SDC timing bug
 2023-10-13 15:32:43 -07:00