David Harris
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7e5b78f240
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plic-s debug
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2022-08-03 12:33:09 +00:00 |
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David Harris
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257107f908
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Partitioned fma into separate files
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2022-08-01 18:07:38 +00:00 |
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David Harris
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75a265159b
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Increased timeout threshold to avoid timeout building riscof tests on slow machine
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2022-07-27 04:05:21 +00:00 |
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David Harris
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9ecef0c4cd
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fixed testbench merge comflict
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2022-07-26 06:21:46 -07:00 |
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David Harris
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2d7f4b133c
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More work toward riscof tests
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2022-07-26 06:19:13 -07:00 |
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David Harris
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766252db1b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-25 23:29:08 +00:00 |
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David Harris
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5c54c5b521
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Added rv32f tests to RV64gc
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2022-07-25 23:29:05 +00:00 |
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David Harris
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c6a58eb5b6
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Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
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2022-07-25 16:23:10 -07:00 |
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Ross Thompson
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8193946996
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-23 08:41:59 -05:00 |
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Katherine Parry
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b3d932cd61
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divider sizes reworked to match book
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2022-07-22 22:02:04 +00:00 |
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Daniel Torres
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24828db612
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changes to test.vh for compatability
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2022-07-22 15:00:48 -07:00 |
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Daniel Torres
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4198145ce2
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added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
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2022-07-22 14:58:55 -07:00 |
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slmnemo
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ba2dcf6da4
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fixed error in tests.vh
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2022-07-22 14:55:55 -07:00 |
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slmnemo
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ec1ed5bd94
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Added UART test to peripheral test
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2022-07-22 14:55:34 -07:00 |
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Daniel Torres
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574e603d69
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 13:52:19 -07:00 |
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Daniel Torres
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139e657fcc
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commented out embench test that should be commented out
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2022-07-22 13:52:13 -07:00 |
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slmnemo
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cb16a75119
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Added PLIC test to regression
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2022-07-22 12:35:37 -07:00 |
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Daniel Torres
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0e75142ef4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 11:16:09 -07:00 |
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Daniel Torres
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95fdd408ee
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commiting current changes to riscof wally tests
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2022-07-22 11:14:04 -07:00 |
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slmnemo
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df568fd202
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Added PLIC and UART tests and new functions to the test library
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2022-07-22 07:10:39 -07:00 |
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Daniel Torres
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8dcb794bbb
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added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
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2022-07-21 20:58:58 -07:00 |
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Daniel Torres
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9421b77613
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 12:50:04 -07:00 |
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Daniel Torres
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a8faddf81f
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removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
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2022-07-21 12:47:51 -07:00 |
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Katherine Parry
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fbe8bb2298
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radix-4 division integrated into srt - not tested
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2022-07-21 19:38:06 +00:00 |
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Katherine Parry
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7950a675ea
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added input enables and improved forwarding
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2022-07-21 01:20:06 +00:00 |
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Daniel Torres
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5b1adc7a67
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commented out embench 2.0 tests
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2022-07-19 13:36:18 -07:00 |
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Katherine Parry
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514674417e
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moved Se into execute stage
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2022-07-19 01:10:10 +00:00 |
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Katherine Parry
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cce5fb8dfd
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moved Ss to execute stage
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2022-07-18 20:48:56 +00:00 |
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Katherine Parry
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7268b4b334
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removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Katherine Parry
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0210718f19
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renamed signals in ocde to match book
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2022-07-18 17:31:17 +00:00 |
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Ross Thompson
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0ef6137ab9
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Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
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2022-07-17 21:05:31 -05:00 |
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Ross Thompson
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8356e5d742
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Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
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2022-07-17 16:20:04 -05:00 |
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Katherine Parry
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5cb9c9f319
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merged floating-point radix-2 divider with radix-4
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2022-07-15 20:16:59 +00:00 |
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Katherine Parry
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2fe8b6e34c
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fixed error in divsqrt
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2022-07-14 18:16:00 +00:00 |
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Katherine Parry
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b874c5c05d
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removed minus 1 case in rounding
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2022-07-13 15:01:38 -07:00 |
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Katherine Parry
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3c1bea1104
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removed warnings and took a mux out of the critical path
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2022-07-12 18:32:17 -07:00 |
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Katherine Parry
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18d7fee541
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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Katherine Parry
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ba339fc794
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-11 18:30:29 -07:00 |
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Katherine Parry
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bea4ec078d
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variable interations implemented in radix-4 divider
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2022-07-11 18:30:21 -07:00 |
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DTowersM
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fe7d03a3da
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added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
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2022-07-11 21:13:09 +00:00 |
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Katherine Parry
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62205ebb3b
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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97e7e619d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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Katherine Parry
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c56fdd7e0f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-08 12:30:50 -07:00 |
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Katherine Parry
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88b4f9b40a
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renamed signals in cvt and prostproc
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2022-07-08 12:30:43 -07:00 |
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David Harris
|
8be1dafbd6
|
Removed testbench code that ignores mismatch on zero signatures
|
2022-07-08 09:17:31 +00:00 |
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DTowersM
|
4786fb9fd6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-07 23:11:35 +00:00 |
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DTowersM
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aa8580b2dc
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new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
|
2022-07-07 23:11:02 +00:00 |
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Katherine Parry
|
75a8cea4e4
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srt divider merged into fpu
|
2022-07-07 16:01:33 -07:00 |
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David Harris
|
f865994ba1
|
fixing port errors
|
2022-07-07 21:57:10 +00:00 |
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Katherine Parry
|
7771f7b3eb
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added load and store test
|
2022-07-07 21:48:51 +00:00 |
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