Katherine Parry
b785b6a9bc
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-06-03 15:34:27 +00:00
Katherine Parry
5ae63f913a
fixed compilation errors
2022-06-03 15:34:17 +00:00
slmnemo
0011a1b269
Changed NO_SPOOFING from 0 to 1 in buildroot-no-trace to better facilitate wally booting linux without following QEMU's trace
2022-06-03 04:55:14 -07:00
David Harris
12399ba924
renamed sim-fp to sim-testfloat
2022-06-02 15:05:29 -07:00
Katherine Parry
c5bde75e30
added createallvectors
2022-06-02 21:56:05 +00:00
slmnemo
b35824eadd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-06-02 12:54:08 -07:00
Katherine Parry
ccda4c771e
fpu paramaterized - except fdivsqrt
2022-06-02 19:50:28 +00:00
slmnemo
568b83a647
Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do"
...
This reverts commit 7d2bfb6db8
2022-06-02 12:45:21 -07:00
slmnemo
581c950193
Revert "Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py"
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This reverts commit 05d14bdb3c
2022-06-02 12:41:01 -07:00
slmnemo
74319c2af6
Revert "Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace"
...
This reverts commit a5490c7096
2022-06-02 12:40:46 -07:00
slmnemo
35caa03e46
Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files
2022-06-02 02:51:51 +00:00
DTowersM
f7491e8445
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-05-31 20:13:41 +00:00
DTowersM
abb6ba97cf
removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM
2022-05-31 20:10:56 +00:00
Katherine Parry
559c0c278e
added unpackinput.sv
2022-05-31 16:18:50 +00:00
slmnemo
3b9ae58f59
Reverted commit 9b55e9da38
2022-05-28 04:00:01 -07:00
slmnemo
2f3689063a
Revert Commit 61ebf68939
2022-05-28 03:35:17 -07:00
slmnemo
9b55e9da38
Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name
2022-05-28 03:16:55 -07:00
slmnemo
61ebf68939
Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do
2022-05-28 03:14:49 -07:00
Katherine Parry
b288f812ab
moved lzc to generic and small optimizations on fcvt
2022-05-27 09:04:02 -07:00
slmnemo
ae460eccd4
Added signal to monitor HBURST and comments for each burst in busdp
2022-05-26 13:35:49 -07:00
slmnemo
466fb71add
added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction
2022-05-25 17:40:57 -07:00
Katherine Parry
c264585fe8
single and double conversions pass all tests
2022-05-25 23:02:02 +00:00
slmnemo
cd9f0cd6bd
fixed a comment spelling typo
2022-05-23 19:24:28 -07:00
Katherine Parry
6bc31f2e78
Fixed unpacker bug LT EQ LE pass testfloat
2022-05-20 17:19:50 +00:00
slmnemo
3b4286ec33
fixed lint autofailing due to no log being produced in regression-wally
2022-05-19 18:30:59 -07:00
slmnemo
6c237e43d8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-05-19 17:51:45 -07:00
slmnemo
a5490c7096
Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace
2022-05-19 17:51:26 -07:00
slmnemo
05d14bdb3c
Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py
2022-05-19 17:50:48 -07:00
slmnemo
7d2bfb6db8
parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do
2022-05-19 16:21:38 -07:00
Katherine Parry
b0881495a9
Bug fixed in unpacker and sub/add/mul tests pass TestFloat
2022-05-19 20:31:23 +00:00
Katherine Parry
cc0ab94ebc
Added fp tests - doesnpass yet
2022-05-19 16:32:30 +00:00
slmnemo
af14c8a064
added instructions to slack notifier
2022-05-18 16:50:31 -07:00
slmnemo
7cd673fa6e
simplified make-tests.sh to run the current makefile in regression
2022-05-17 17:29:34 -07:00
slmnemo
1131d41343
added wkdir in regression so regression runs out of box (assuming the old version of arch tests)
2022-05-17 20:32:38 +00:00
Kip Macsai-Goren
25ad39939f
put privileged tests back into rv32/64gc
2022-05-04 21:20:25 +00:00
David Harris
9c4de0e9c1
FPU generates illegal instruction if MSTATUS.FS = 00
2022-05-03 11:56:31 +00:00
David Harris
dee32f70bf
Switched to behavioral comparator for best PPA
2022-05-03 11:00:39 +00:00
Kip Macsai-Goren
89cce88d33
fixed incorrect configs in regression
2022-04-25 19:28:47 +00:00
Kip Macsai-Goren
0f4ca62157
added working tests to test list, updated regression for new configs
2022-04-25 19:18:15 +00:00
David Harris
03f84bf11c
Extended sim time to fully boot Linux. Added comments to hazard unit
2022-04-24 13:51:00 +00:00
Ross Thompson
165a36acac
Modified wally-pipelined.do for no trace linux sim.
2022-04-21 09:52:33 -05:00
David Harris
861fbd698b
Run 4M instructions in buildroot test to get through kernel & VirtMem startup
2022-04-18 01:29:38 +00:00
David Harris
83d283354c
Added comments in fcvt
2022-04-17 16:53:10 +00:00
Ross Thompson
238cc9f9fd
Commented output power analysis to speed simulation.
2022-04-16 15:32:59 -05:00
Ross Thompson
f995ec2a54
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-10 13:41:27 -05:00
Ross Thompson
c3d9eafe60
Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
2022-04-10 13:27:54 -05:00
bbracker
3b6cb5f0ba
small signs of life on new interrupt spoofing
2022-04-08 12:32:30 -07:00
David Harris
c22d6f2848
Added bootmem source ccode
2022-04-05 23:22:53 +00:00
Ross Thompson
d83db2cde5
Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
2022-04-04 09:57:26 -05:00
Ross Thompson
e7abcd862f
fpga simulation works again.
2022-04-03 17:31:07 -05:00
Kip Macsai-Goren
cdea062287
added RV64IA config to have a config without compressed instructions
2022-04-02 18:24:08 +00:00
Ross Thompson
987236e463
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-01 17:18:25 -05:00
Ross Thompson
57eba4355e
Updated the fpga test bench.
2022-04-01 17:14:47 -05:00
bbracker
cbff9a7755
expand WALLY-PERIPH test to use SEIP on PLIC context 1
2022-03-31 18:02:06 -07:00
Kip Macsai-Goren
2e68ab7bb4
added test config that doesn't use compressed instructions for privileged tests
2022-03-28 19:12:31 +00:00
Skylar Litz
29d1f64588
add AtemptedInstructionCount signal
2022-03-26 21:28:57 +00:00
Skylar Litz
bb8587e06f
update to match new filesystem organization
2022-03-26 21:28:32 +00:00
bbracker
efb5d1dbc0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-04 00:06:27 +00:00
bbracker
443dd40ea8
remove imperas32p tests
2022-03-04 00:06:18 +00:00
David Harris
545f569f78
Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
2022-03-03 15:38:08 +00:00
bbracker
e28ca531e0
fix peripheral test and add it to regression
2022-03-02 23:44:39 +00:00
bbracker
c1290d493f
add CSRs to waveview
2022-03-02 18:31:10 +00:00
bbracker
d7b8c9d877
add rv32a tests to regression
2022-03-02 17:54:55 +00:00
bbracker
5f5cc514b8
fix buildroot checkpointing and add it back to regression
2022-03-02 16:00:19 +00:00
bbracker
4f22a55dd4
add LRSC test and add wally64a to regression
2022-03-02 07:09:37 +00:00
bbracker
41b3912abc
buildroot graphical sim bugfix
2022-03-01 03:24:23 +00:00
bbracker
04ace8c154
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
2022-03-01 03:11:43 +00:00
bbracker
d620fb4442
deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
2022-03-01 00:37:46 +00:00
David Harris
046259cff8
Moved regression work directories to regression/wkdir to reduce clutter
2022-02-27 17:35:09 +00:00
David Harris
eb0bbacd43
Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue
2022-02-27 15:12:10 +00:00
David Harris
eda60a7691
Moved Softfloat / TestFloat
2022-02-26 19:17:32 +00:00
Ross Thompson
d331b9f29d
Fixed "bug" with wally-pipelined.do
2022-02-22 22:19:25 -06:00
bbracker
6caa97bb26
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
Ross Thompson
ad237b3ce5
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
0eec096474
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
Ross Thompson
2fc7dc3e57
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
eafd52e2bc
Added additional suppresses to vsim command incase buildroot files are missing.
2022-02-16 17:05:54 -06:00
Skylar Litz
0c69d3291d
update bugfinder script to new file organization
2022-02-15 22:58:18 +00:00
Ross Thompson
a440bc2ac5
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
b1cba4be2b
Updates to linux wave.
2022-02-11 13:28:18 -06:00
Ross Thompson
9145a96b53
Updated linux wave.
2022-02-11 13:15:42 -06:00
Ross Thompson
3f4ae91468
linux wave cleanup.
2022-02-11 10:48:45 -06:00
Ross Thompson
2f2a4f4500
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
Ross Thompson
9ad4523b9d
Updated wave files to reflect recent changes.
2022-02-10 17:52:19 -06:00
Ross Thompson
327a05c9d8
Added commented out commands to generate saif file from vsim.
2022-02-09 18:40:45 -06:00
David Harris
096242a6d8
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
David Harris
72c2166223
Lab 3 file cleanup
2022-02-08 10:26:37 +00:00
David Harris
d0c40cca7a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-07 14:43:31 +00:00
David Harris
0feb624bab
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
bbracker
fc2e3d1fbf
remove rv32e from regression because it is broken; goes with previous commit
2022-02-05 23:05:21 +00:00
David Harris
0dd8c719ad
Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
2022-02-05 05:35:51 +00:00
David Harris
f7d6939d9b
Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts
2022-02-05 05:28:40 +00:00
David Harris
581fbb7d13
Modified wally-pipelined-batch.do to handle buildroot
2022-02-05 05:07:07 +00:00
David Harris
23868a33bc
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
David Harris
16b5fee795
RV32e tests
2022-02-04 14:30:36 +00:00
David Harris
1c049f1f67
renamed configs
2022-02-03 23:36:41 +00:00
David Harris
e92461159d
cache cleanup
2022-02-03 15:36:11 +00:00
Ross Thompson
4a5aa43716
Merge branch 'makefiles' into main
2022-02-03 08:33:50 -06:00
