cvw/pipelined/regression
2022-04-25 19:18:15 +00:00
..
slack-notifier
wave-dos
buildrootBugFinder.py update to match new filesystem organization 2022-03-26 21:28:32 +00:00
fpga-wave.do Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
lint-wally
linux-wave.do small signs of life on new interrupt spoofing 2022-04-08 12:32:30 -07:00
make-tests.sh
Makefile Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
makefile-memfile Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
regression-wally added working tests to test list, updated regression for new configs 2022-04-25 19:18:15 +00:00
sim-buildroot switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv 2022-03-01 03:11:43 +00:00
sim-buildroot-batch switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv 2022-03-01 03:11:43 +00:00
sim-coremark-batch
sim-fp64
sim-fp64-batch
sim-wally
sim-wally-batch
wally-coremark.do
wally-fp64-batch.do
wally-fp64.do
wally-harvard.do
wally-pipelined-batch.do Commented output power analysis to speed simulation. 2022-04-16 15:32:59 -05:00
wally-pipelined-fpga.do fpga simulation works again. 2022-04-03 17:31:07 -05:00
wally-pipelined.do Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
wave-all.do
wave-coremark.do
wave.do expand WALLY-PERIPH test to use SEIP on PLIC context 1 2022-03-31 18:02:06 -07:00