David Harris
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b89fe9989e
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Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED
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2023-01-28 18:52:00 -08:00 |
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David Harris
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fa3643a064
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Renamed BUS to BUS_SUPPORTED
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2023-01-28 18:35:53 -08:00 |
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David Harris
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8a96dcf0ae
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Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED
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2023-01-28 18:17:42 -08:00 |
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David Harris
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a99fc74976
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Removed integer from localparams
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2023-01-27 14:40:06 -08:00 |
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Ross Thompson
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07308e2c14
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Removed mark_debug from all source code.
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2023-01-20 18:47:36 -06:00 |
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Ross Thompson
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b8a699270e
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More cleanup and formatting.
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2023-01-20 12:34:40 -06:00 |
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Ross Thompson
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f1049be6c1
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More cleanup and formatting.
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2023-01-20 12:09:21 -06:00 |
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Ross Thompson
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4a2d02ab28
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Formatting.
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2023-01-20 11:51:10 -06:00 |
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Ross Thompson
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999477bb02
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Formatting and name changes.
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2023-01-19 14:16:29 -06:00 |
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Ross Thompson
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21b2b10e78
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Formatting spillsupport.
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2023-01-18 19:25:54 -06:00 |
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Ross Thompson
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63577cbf4a
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Cleanup dtim and irom.
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2023-01-18 18:44:30 -06:00 |
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Ross Thompson
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c5c4a3c011
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Formatting
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2023-01-18 16:58:03 -06:00 |
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Ross Thompson
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c3096eea2a
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Cleaned up ahbcacheinterface.
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2023-01-17 22:13:56 -06:00 |
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Ross Thompson
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4720b28272
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Formatting progress.
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2023-01-17 22:10:31 -06:00 |
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Ross Thompson
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8e3e8591a6
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Removed 1 bit from instruction classification.
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2023-01-13 15:19:53 -06:00 |
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sarah-harris
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3b363f5f9d
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privilege unit -> privileged unit in ifu.sv
privilege unit -> privileged unit in ifu.sv
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2023-01-11 16:33:08 -08:00 |
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David Harris
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7d93659f6b
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changed name to CORE-V-WALLY
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2023-01-11 15:15:08 -08:00 |
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David Harris
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b911056e66
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Changed Wally to CORE-V Wally
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2023-01-11 14:03:44 -08:00 |
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David Harris
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e92cffbb5e
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Changed MIT license to Solderpad License
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2023-01-10 11:35:20 -08:00 |
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David Harris
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9bdf79bfe6
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Removed unused signals; added check for atomic in pmachecker
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2023-01-07 05:59:56 -08:00 |
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David Harris
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d1839b6db2
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Remove conditional from inside decompress module
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2023-01-07 05:51:47 -08:00 |
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David Harris
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0a011f4548
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Remove unused signals
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2023-01-07 05:46:22 -08:00 |
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Ross Thompson
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e34f80db2f
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More branch predictor cleanup.
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2023-01-05 17:19:27 -06:00 |
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Ross Thompson
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3637067ace
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Officially added global history with speculation to types of branch predictors.
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2023-01-05 14:04:09 -06:00 |
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Ross Thompson
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8ca6c1255e
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More branch predictor cleanup.
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2023-01-05 13:36:51 -06:00 |
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Ross Thompson
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f8c656f1e0
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Simiplified global history branch predictor.
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2023-01-04 23:41:55 -06:00 |
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Ross Thompson
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1f42098758
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Added about moving decompressed config generate.
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2022-12-27 15:04:55 -06:00 |
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Ross Thompson
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1d11ff6153
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Added missing assignment for no branch predictor mode.
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2022-12-24 17:08:29 -06:00 |
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Ross Thompson
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b5a85b55f1
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
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2022-12-23 15:10:37 -06:00 |
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Ross Thompson
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6b105bd217
|
Renamed IFU and LSU stalls.
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2022-12-22 21:56:33 -06:00 |
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Ross Thompson
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ce7e1073fa
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Success we've replaced TrapM with FlushD in the IFU.
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2022-12-22 21:36:49 -06:00 |
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Ross Thompson
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942acb354e
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Closing in on icache flushed by FlushD rather than TrapM.
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2022-12-22 20:19:09 -06:00 |
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Ross Thompson
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47d61984ad
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First pass at resolving ifu flush on trap rather than FlushD.
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2022-12-22 15:53:06 -06:00 |
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Ross Thompson
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0cb2cf9a5b
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Changed GatedStallF to GatedStallD.
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2022-12-21 16:12:55 -06:00 |
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Ross Thompson
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2b1e9f8bed
|
The optimzied PC+2/4 logic still hanges on wally32priv.
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2022-12-21 09:19:34 -06:00 |
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Ross Thompson
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a2329c8e9d
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Renamed PCPlusUpperF to PCPlus4F.
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2022-12-21 09:18:30 -06:00 |
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Ross Thompson
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3fc121ef70
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Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
Switched to even simplier PC+2/4 logic.
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2022-12-21 09:00:09 -06:00 |
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Ross Thompson
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bc5d5e902a
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Comments about PC+2/4.
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2022-12-21 08:35:43 -06:00 |
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Ross Thompson
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6152c028db
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-20 18:09:37 -06:00 |
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Ross Thompson
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cba2ed64e5
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Moved privileged pc logic into privileged unit.
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2022-12-20 17:55:45 -06:00 |
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David Harris
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07dc11a508
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IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI
|
2022-12-20 15:38:30 -08:00 |
|
Ross Thompson
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b4bdf446cc
|
Implement FENCE.I as NOP when ZIFENCEI is not supported.
|
2022-12-20 17:34:11 -06:00 |
|
Ross Thompson
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637df763ca
|
Renumbered bits for PCPlusUpper.
|
2022-12-20 16:33:49 -06:00 |
|
Ross Thompson
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d35fc5e2a6
|
Reorganized IFU PCNextF logic.
|
2022-12-20 12:58:54 -06:00 |
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Ross Thompson
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d18ef45c18
|
More bp/ifu pcmux cleanup.
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2022-12-19 23:16:58 -06:00 |
|
Ross Thompson
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761cf54dcc
|
Moved more muxes inside bp.
|
2022-12-19 22:51:55 -06:00 |
|
Ross Thompson
|
0097c166d6
|
Begin cleanup of ifu. partial move of pc muxes inside bp.
|
2022-12-19 22:46:11 -06:00 |
|
David Harris
|
2393915bf2
|
Simplified InstrRawD register
|
2022-12-19 15:18:42 -08:00 |
|
Ross Thompson
|
c253b882be
|
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
|
2022-12-15 09:53:35 -06:00 |
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Ross Thompson
|
dbc3dac03d
|
Removed unused flushf.
|
2022-12-11 16:28:11 -06:00 |
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