Commit Graph

229 Commits

Author SHA1 Message Date
David Harris
b89fe9989e Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED 2023-01-28 18:52:00 -08:00
David Harris
fa3643a064 Renamed BUS to BUS_SUPPORTED 2023-01-28 18:35:53 -08:00
David Harris
8a96dcf0ae Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED 2023-01-28 18:17:42 -08:00
David Harris
a99fc74976 Removed integer from localparams 2023-01-27 14:40:06 -08:00
Ross Thompson
07308e2c14 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
Ross Thompson
b8a699270e More cleanup and formatting. 2023-01-20 12:34:40 -06:00
Ross Thompson
f1049be6c1 More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
4a2d02ab28 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
999477bb02 Formatting and name changes. 2023-01-19 14:16:29 -06:00
Ross Thompson
21b2b10e78 Formatting spillsupport. 2023-01-18 19:25:54 -06:00
Ross Thompson
63577cbf4a Cleanup dtim and irom. 2023-01-18 18:44:30 -06:00
Ross Thompson
c5c4a3c011 Formatting 2023-01-18 16:58:03 -06:00
Ross Thompson
c3096eea2a Cleaned up ahbcacheinterface. 2023-01-17 22:13:56 -06:00
Ross Thompson
4720b28272 Formatting progress. 2023-01-17 22:10:31 -06:00
Ross Thompson
8e3e8591a6 Removed 1 bit from instruction classification. 2023-01-13 15:19:53 -06:00
sarah-harris
3b363f5f9d privilege unit -> privileged unit in ifu.sv
privilege unit -> privileged unit in ifu.sv
2023-01-11 16:33:08 -08:00
David Harris
7d93659f6b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
David Harris
b911056e66 Changed Wally to CORE-V Wally 2023-01-11 14:03:44 -08:00
David Harris
e92cffbb5e Changed MIT license to Solderpad License 2023-01-10 11:35:20 -08:00
David Harris
9bdf79bfe6 Removed unused signals; added check for atomic in pmachecker 2023-01-07 05:59:56 -08:00
David Harris
d1839b6db2 Remove conditional from inside decompress module 2023-01-07 05:51:47 -08:00
David Harris
0a011f4548 Remove unused signals 2023-01-07 05:46:22 -08:00
Ross Thompson
e34f80db2f More branch predictor cleanup. 2023-01-05 17:19:27 -06:00
Ross Thompson
3637067ace Officially added global history with speculation to types of branch predictors. 2023-01-05 14:04:09 -06:00
Ross Thompson
8ca6c1255e More branch predictor cleanup. 2023-01-05 13:36:51 -06:00
Ross Thompson
f8c656f1e0 Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
Ross Thompson
1f42098758 Added about moving decompressed config generate. 2022-12-27 15:04:55 -06:00
Ross Thompson
1d11ff6153 Added missing assignment for no branch predictor mode. 2022-12-24 17:08:29 -06:00
Ross Thompson
b5a85b55f1 Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
6b105bd217 Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
ce7e1073fa Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
Ross Thompson
942acb354e Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
Ross Thompson
47d61984ad First pass at resolving ifu flush on trap rather than FlushD. 2022-12-22 15:53:06 -06:00
Ross Thompson
0cb2cf9a5b Changed GatedStallF to GatedStallD. 2022-12-21 16:12:55 -06:00
Ross Thompson
2b1e9f8bed The optimzied PC+2/4 logic still hanges on wally32priv. 2022-12-21 09:19:34 -06:00
Ross Thompson
a2329c8e9d Renamed PCPlusUpperF to PCPlus4F. 2022-12-21 09:18:30 -06:00
Ross Thompson
3fc121ef70 Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
Switched to even simplier PC+2/4 logic.
2022-12-21 09:00:09 -06:00
Ross Thompson
bc5d5e902a Comments about PC+2/4. 2022-12-21 08:35:43 -06:00
Ross Thompson
6152c028db Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 18:09:37 -06:00
Ross Thompson
cba2ed64e5 Moved privileged pc logic into privileged unit. 2022-12-20 17:55:45 -06:00
David Harris
07dc11a508 IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI 2022-12-20 15:38:30 -08:00
Ross Thompson
b4bdf446cc Implement FENCE.I as NOP when ZIFENCEI is not supported. 2022-12-20 17:34:11 -06:00
Ross Thompson
637df763ca Renumbered bits for PCPlusUpper. 2022-12-20 16:33:49 -06:00
Ross Thompson
d35fc5e2a6 Reorganized IFU PCNextF logic. 2022-12-20 12:58:54 -06:00
Ross Thompson
d18ef45c18 More bp/ifu pcmux cleanup. 2022-12-19 23:16:58 -06:00
Ross Thompson
761cf54dcc Moved more muxes inside bp. 2022-12-19 22:51:55 -06:00
Ross Thompson
0097c166d6 Begin cleanup of ifu. partial move of pc muxes inside bp. 2022-12-19 22:46:11 -06:00
David Harris
2393915bf2 Simplified InstrRawD register 2022-12-19 15:18:42 -08:00
Ross Thompson
c253b882be Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage. 2022-12-15 09:53:35 -06:00
Ross Thompson
dbc3dac03d Removed unused flushf. 2022-12-11 16:28:11 -06:00