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373 lines
18 KiB
Systemverilog
373 lines
18 KiB
Systemverilog
///////////////////////////////////////////
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// ifu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Instrunction Fetch Unit
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// PC, branch prediction, instruction cache
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ifu (
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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// Bus interface
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(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR,
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(* mark_debug = "true" *) output logic IFUStallF,
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(* mark_debug = "true" *) output logic [2:0] IFUHBURST,
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(* mark_debug = "true" *) output logic [1:0] IFUHTRANS,
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(* mark_debug = "true" *) output logic [2:0] IFUHSIZE,
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(* mark_debug = "true" *) output logic IFUHWRITE,
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(* mark_debug = "true" *) input logic IFUHREADY,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
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// Execute
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output logic [`XLEN-1:0] PCLinkE,
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input logic PCSrcE,
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input logic [`XLEN-1:0] IEUAdrE,
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output logic [`XLEN-1:0] PCE,
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output logic BPPredWrongE,
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// Mem
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output logic CommittedF,
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input logic [`XLEN-1:0] UnalignedPCNextF,
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output logic [`XLEN-1:0] PCNext2F,
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input logic CSRWriteFenceM,
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input logic InvalidateICacheM,
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output logic [31:0] InstrD, InstrM,
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output logic [`XLEN-1:0] PCM,
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// branch predictor
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output logic [4:0] InstrClassM,
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output logic DirPredictionWrongM,
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output logic BTBPredPCWrongM,
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output logic RASPredPCWrongM,
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output logic PredictionInstrClassWrongM,
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// Faults
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input logic IllegalBaseInstrFaultD,
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output logic InstrPageFaultF,
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output logic IllegalIEUInstrFaultD,
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output logic InstrMisalignedFaultM,
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// mmu management
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] PTE,
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input logic [1:0] PageType,
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic ITLBWriteF, sfencevmaM,
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output logic ITLBMissF, InstrDAPageFaultF,
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output logic InstrAccessFaultF,
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output logic ICacheAccess,
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output logic ICacheMiss
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);
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(* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF;
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logic BranchMisalignedFaultE;
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logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
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logic [`XLEN-1:2] PCPlus4F;
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logic CompressedF;
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logic [31:0] InstrRawD, InstrRawF, IROMInstrF, ICacheInstrF;
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logic [31:0] FinalInstrRawF;
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logic [1:0] IFURWF;
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logic [31:0] InstrE;
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logic [`XLEN-1:0] PCD;
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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logic [31:0] NextInstrD, NextInstrE;
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logic [`XLEN-1:0] NextValidPCE;
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(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPF; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
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logic [`XLEN+1:0] PCFExt;
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logic CacheableF;
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logic [`XLEN-1:0] PCNextFSpill;
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logic [`XLEN-1:0] PCFSpill;
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logic SelNextSpillF;
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logic ICacheFetchLine;
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logic BusStall;
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logic ICacheStallF, IFUCacheBusStallD;
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logic GatedStallD;
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(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF;
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// branch predictor signal
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logic [`XLEN-1:0] PCNext1F, PCNext0F;
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logic BusCommittedF, CacheCommittedF;
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logic SelIROM;
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assign PCFExt = {2'b00, PCFSpill};
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Spill Support
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(`C_SUPPORTED) begin : SpillSupport
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spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(FlushD), .PCF, .PCPlus4F, .PCNextF, .InstrRawF(InstrRawF),
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.InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill,
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.SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
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end else begin : NoSpillSupport
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assign PCNextFSpill = PCNextF;
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assign PCFSpill = PCF;
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assign PostSpillInstrRawF = InstrRawF;
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assign {SelNextSpillF, CompressedF} = 0;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Memory management
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////////////////////////////////////////////////////////////////////////////////////////////////
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if(`ZICSR_SUPPORTED == 1) begin : immu
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///////////////////////////////////////////
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// sfence.vma causes TLB flushes
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///////////////////////////////////////////
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// sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
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// In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
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// But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and
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// the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush
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// after a cycle AND pulse it for another cycle on any further back-to-back sfences.
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logic StallMQ, TLBFlush;
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flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
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assign TLBFlush = sfencevmaM & ~StallMQ;
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mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
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immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation(1'b0),
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.VAdr(PCFExt),
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.Size(2'b10),
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.PTE(PTE),
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.PageTypeWriteVal(PageType),
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.TLBWrite(ITLBWriteF),
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.TLBFlush,
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.PhysicalAddress(PCPF),
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.TLBMiss(ITLBMissF),
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.Cacheable(CacheableF), .Idempotent(), .SelTIM(SelIROM),
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.InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(),
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.InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(),
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.LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),
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.DAPageFault(InstrDAPageFaultF),
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.AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0),
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
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end else begin
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assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrDAPageFaultF} = '0;
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assign PCPF = PCFExt[`PA_BITS-1:0];
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assign CacheableF = '1;
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assign SelIROM = '0;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Memory
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////////////////////////////////////////////////////////////////////////////////////////////////
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// CommittedM tells the CPU's privilege unit the current instruction
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// in the memory stage is a memory operaton and that memory operation is either completed
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// or is partially executed. Partially completed memory operations need to prevent an interrupts.
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// There is not a clean way to restore back to a partial executed instruction. CommiteedM will
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// delay the interrupt until the LSU is in a clean state.
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assign CommittedF = CacheCommittedF | BusCommittedF;
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logic IgnoreRequest;
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assign IgnoreRequest = ITLBMissF | FlushD;
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// The IROM uses untranslated addresses, so it is not compatible with virtual memory.
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if (`IROM_SUPPORTED) begin : irom
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assign IFURWF = 2'b10;
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irom irom(.clk, .ce(~GatedStallD | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF));
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end else begin
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assign IFURWF = 2'b10;
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end
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if (`BUS) begin : bus
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// **** must fix words per line vs beats per line as in lsu.
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localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
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localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
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if(`ICACHE) begin : icache
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localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
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logic [LINELEN-1:0] FetchBuffer;
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logic [`PA_BITS-1:0] ICacheBusAdr;
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logic ICacheBusAck;
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logic [1:0] CacheBusRW, BusRW, CacheRWF;
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//assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF} & ~{SelIROM, SelIROM};
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assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
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assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
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icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
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.FetchBuffer, .CacheBusAck(ICacheBusAck),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
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.CacheBusRW,
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.ReadDataWord(ICacheInstrF),
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.SelHPTW('0),
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.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
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.ByteMask('0), .BeatCount('0), .SelBusBeat('0),
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.CacheWriteData('0),
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.CacheRW(CacheRWF),
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.CacheAtomic('0), .FlushCache('0),
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.NextAdr(PCNextFSpill[11:0]),
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.PAdr(PCPF),
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.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
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ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
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ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
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.HRDATA,
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.Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
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.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
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.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
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.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
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.FetchBuffer, .PAdr(PCPF),
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.BusRW, .Stall(GatedStallD),
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.BusStall, .BusCommitted(BusCommittedF));
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mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF),
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.s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0]));
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end else begin : passthrough
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assign IFUHADDR = PCPF;
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logic [31:0] FetchBuffer;
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logic [1:0] BusRW;
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assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0;
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assign IFUHSIZE = 3'b010;
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ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY),
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.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
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.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
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.Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
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assign CacheCommittedF = '0;
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if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF);
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else assign InstrRawF = FetchBuffer;
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assign IFUHBURST = 3'b0;
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assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0;
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assign {ICacheMiss, ICacheAccess} = '0;
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end
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end else begin : nobus // block: bus
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assign {BusStall, CacheCommittedF} = '0;
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assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
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assign InstrRawF = IROMInstrF;
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end
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assign IFUCacheBusStallD = ICacheStallF | BusStall;
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assign IFUStallF = IFUCacheBusStallD | SelNextSpillF;
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assign GatedStallD = StallD & ~SelNextSpillF;
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flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
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////////////////////////////////////////////////////////////////////////////////////////////////
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// PCNextF logic
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////////////////////////////////////////////////////////////////////////////////////////////////
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if(`ZICSR_SUPPORTED | `ZIFENCEI_SUPPORTED)
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mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F));
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else assign PCNext2F = PCNext1F;
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assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
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flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);
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// pcadder
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// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
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assign PCPlus4F = PCF[`XLEN-1:2] + 1; // add 4 to PC
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// choose PC+2 or PC+4 based on CompressedF, which arrives later.
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// Speeds up critical path as compared to selecting adder input based on CompressedF
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// *** consider gating PCPlus4F to provide the reset.
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/* -----\/----- EXCLUDED -----\/-----
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assign PCPlus2or4F[0] = '0;
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assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]);
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assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlus4F;
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0];
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-----/\----- EXCLUDED -----/\----- */
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// *** There is actually a bug in the regression test. We fetched an address which returns data with
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// an X. This version of the code does not die because if CompressedF is an X it just defaults to the last
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// option. The above code would work, but propagates the x.
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always_comb
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if(reset) PCPlus2or4F = '0;
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else if (CompressedF) // add 2
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if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00};
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else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
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else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Branch and Jump Predictor
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////////////////////////////////////////////////////////////////////////////////////////////////
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if (`BPRED_ENABLED) begin : bpred
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bpred bpred(.clk, .reset,
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.StallF, .StallD, .StallE, .StallM, .StallW,
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.FlushD, .FlushE, .FlushM, .FlushW,
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.InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
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.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
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.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
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end else begin : bpred
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mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F));
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assign BPPredWrongE = PCSrcE;
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assign {InstrClassM, DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM} = '0;
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assign PCNext0F = PCPlus2or4F;
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assign NextValidPCE = PCE;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Decode stage pipeline register and compressed instruction decoding.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Decode stage pipeline register and logic
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flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
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// expand 16-bit compressed instructions to 32 bits
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if (`C_SUPPORTED) begin
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logic IllegalCompInstrD;
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decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
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assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
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end else begin
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assign InstrD = InstrRawD;
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assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD;
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end
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// Misaligned PC logic
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// Instruction address misalignement only from br/jal(r) instructions.
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// instruction address misalignment is generated by the target of control flow instructions, not
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// the fetch itself.
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// xret and Traps both cannot produce instruction misaligned.
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// xret: mepc is an MXLEN-bit read/write register formatted as shown in Figure 3.21.
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// The low bit of mepc (mepc[0]) is always zero. On implementations that support
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// only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
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// Spec 3.1.14
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// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
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assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
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flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
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// Instruction and PC/PCLink pipeline registers
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mux2 #(32) FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
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mux2 #(32) FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
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flopenr #(32) InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
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flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
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flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
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flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
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flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
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flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
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||
endmodule
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