Katherine Parry
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7950a675ea
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added input enables and improved forwarding
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2022-07-21 01:20:06 +00:00 |
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Daniel Torres
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5b1adc7a67
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commented out embench 2.0 tests
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2022-07-19 13:36:18 -07:00 |
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Katherine Parry
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514674417e
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moved Se into execute stage
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2022-07-19 01:10:10 +00:00 |
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Katherine Parry
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cce5fb8dfd
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moved Ss to execute stage
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2022-07-18 20:48:56 +00:00 |
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Katherine Parry
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7268b4b334
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removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Katherine Parry
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0210718f19
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renamed signals in ocde to match book
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2022-07-18 17:31:17 +00:00 |
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Katherine Parry
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5cb9c9f319
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merged floating-point radix-2 divider with radix-4
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2022-07-15 20:16:59 +00:00 |
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Katherine Parry
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2fe8b6e34c
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fixed error in divsqrt
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2022-07-14 18:16:00 +00:00 |
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Katherine Parry
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b874c5c05d
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removed minus 1 case in rounding
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2022-07-13 15:01:38 -07:00 |
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Katherine Parry
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3c1bea1104
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removed warnings and took a mux out of the critical path
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2022-07-12 18:32:17 -07:00 |
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Katherine Parry
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18d7fee541
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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Katherine Parry
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ba339fc794
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-11 18:30:29 -07:00 |
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Katherine Parry
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bea4ec078d
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variable interations implemented in radix-4 divider
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2022-07-11 18:30:21 -07:00 |
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DTowersM
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fe7d03a3da
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added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
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2022-07-11 21:13:09 +00:00 |
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Katherine Parry
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62205ebb3b
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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97e7e619d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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Katherine Parry
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c56fdd7e0f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-08 12:30:50 -07:00 |
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Katherine Parry
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88b4f9b40a
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renamed signals in cvt and prostproc
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2022-07-08 12:30:43 -07:00 |
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David Harris
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8be1dafbd6
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Removed testbench code that ignores mismatch on zero signatures
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2022-07-08 09:17:31 +00:00 |
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DTowersM
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4786fb9fd6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-07 23:11:35 +00:00 |
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DTowersM
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aa8580b2dc
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new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
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2022-07-07 23:11:02 +00:00 |
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Katherine Parry
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75a8cea4e4
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srt divider merged into fpu
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2022-07-07 16:01:33 -07:00 |
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David Harris
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f865994ba1
|
fixing port errors
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2022-07-07 21:57:10 +00:00 |
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Katherine Parry
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7771f7b3eb
|
added load and store test
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2022-07-07 21:48:51 +00:00 |
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DTowersM
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5dfff900b1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-06 23:44:27 +00:00 |
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DTowersM
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67c5d66209
|
added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu
|
2022-07-06 23:43:57 +00:00 |
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David Harris
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f5bdbbe219
|
Removed sig4 spurious message from testbench
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2022-07-05 03:27:14 +00:00 |
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Katherine Parry
|
2fc795ca70
|
added missing files
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2022-07-03 21:40:47 -07:00 |
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Katherine Parry
|
8ac722f693
|
Renaming signals to match chapter
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2022-07-03 12:26:22 -07:00 |
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Daniel Torres
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d1eebac73f
|
reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished
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2022-06-29 12:32:30 -07:00 |
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Daniel Torres
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2ae22ac6cb
|
added changes to testbench, tests and riscof for additional riscof compatability
|
2022-06-29 12:23:40 -07:00 |
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slmnemo
|
228028c837
|
Add CLINT tests from book
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2022-06-27 20:09:58 -07:00 |
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Katherine Parry
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a5fb60eb1a
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radix-4 early termination working for special cases - not working completely
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2022-06-27 20:43:55 +00:00 |
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Katherine Parry
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70a1bb8377
|
fixed commented out error and removed killprod from result selection
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2022-06-25 01:42:23 +00:00 |
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Katherine Parry
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9eefba5b58
|
added denormal input handeling - radix 4
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2022-06-24 19:41:40 +00:00 |
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Katherine Parry
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de71773d69
|
added radix-4 0/d handling
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2022-06-23 22:36:19 +00:00 |
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Katherine Parry
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a5fc6757a1
|
generate qsel4 in verilog
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2022-06-23 21:38:04 +00:00 |
|
Katherine Parry
|
d7a363aaa7
|
fixt lint error
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2022-06-23 16:11:50 +00:00 |
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Katherine Parry
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1612daa294
|
Testfloat running division - not passing
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2022-06-23 00:07:34 +00:00 |
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David Harris
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d865a1ce95
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-21 22:45:28 +00:00 |
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slmnemo
|
80a57d0469
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-21 02:16:26 -07:00 |
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slmnemo
|
b2cea45de0
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
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Katherine Parry
|
03d823f5d7
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
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Daniel Torres
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397783812d
|
embench and testbench now support running both O2 and Os build variations without overwriting one another
|
2022-06-17 21:15:42 -07:00 |
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Daniel Torres
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1d4c543f71
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
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0ede7c412e
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
475220a5ff
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
David Harris
|
f6e52c7f08
|
Removed testbench.sv.bak
|
2022-06-14 22:04:38 +00:00 |
|
DTowersM
|
7c0f4dd954
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 23:34:35 +00:00 |
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DTowersM
|
39ed36d0ba
|
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
|
2022-06-13 23:23:57 +00:00 |
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