Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-23 04:54:29 +00:00
Code Issues Packages Projects Releases Wiki Activity
5,592 Commits 4 Branches 2 Tags 52 MiB
77ba71be71
Commit Graph

3 Commits

Author SHA1 Message Date
Ross Thompson
659b511616 Lee Moore found another bug using imperas. 
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
 2023-02-02 23:52:21 -06:00
Ross Thompson
ad570a4c47 Test commit. please merge. 2023-01-23 12:53:31 -06:00
Ross Thompson
c8e6884926 Fixed bug. 
It was possible for DTLBMissM to prevent a dcache flush.
 2022-02-11 14:00:01 -06:00