mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
6 lines
146 B
Plaintext
6 lines
146 B
Plaintext
1. [X] Cache is suppressing d cache flush if there is a dtlb miss.
|
|
1. Fixed by disabling mmu's address translation on flush.
|
|
|
|
|
|
2. Test commit.
|