165 Commits

Author	SHA1	Message	Date
David Harris	761dae72fe	Config file & wally-riscv-arch-test cleanup	2022-02-02 16:35:52 +00:00
Ross Thompson	2d8b0aa650	Modified makefiles to generate function address to name mappings for modelsim.	2022-02-01 18:25:03 -06:00
Ross Thompson	058b368a22	Improved function_radix to not printout warnings when no valid function is found.	2022-02-01 18:03:09 -06:00
Ross Thompson	138b17a399	Setup the main regression test to be able to handle coremark.	2022-02-01 17:00:11 -06:00
Ross Thompson	910d16b642	More cleanup of IFU.	2022-02-01 14:32:27 -06:00
Ross Thompson	dce9ee12b4	IFU and LSU now share the same busdp module.	2022-01-31 16:25:41 -06:00
Ross Thompson	a04aa283cb	partial ifu cleanup.	2022-01-31 16:08:53 -06:00
Ross Thompson	b05abc1795	cleanup.	2022-01-31 13:29:04 -06:00
Ross Thompson	c1311ca56a	Fixed modelsim warning with linux simulation.	2022-01-31 12:57:02 -06:00
Ross Thompson	d2ab17e1af	Repaired linux-wave.do	2022-01-31 12:54:18 -06:00
Ross Thompson	3475e142a5	Repaired wavefile and fixed modelsim warning.	2022-01-31 12:34:17 -06:00
Ross Thompson	1476a79ea2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-31 12:17:37 -06:00
Ross Thompson	fa8914a830	Cleanup busdp.	2022-01-31 12:17:07 -06:00
Ross Thompson	7c3d6bbdb4	Moved lsu virtual memory logic into separate module.	2022-01-31 11:56:03 -06:00
Ross Thompson	e35a8299ec	Encapsulated dtim.	2022-01-31 11:23:55 -06:00
Ross Thompson	dbe40856a2	Removed unused signals in the LSU.	2022-01-31 10:35:35 -06:00
Ross Thompson	bfbc31d184	Moved atomic logic to own module.	2022-01-31 10:28:12 -06:00
Ross Thompson	ef770fd183	Encapsulated the bus data path into a separate module.	2022-01-31 10:15:48 -06:00
Kip Macsai-Goren	1077cf08b0	added machine info test that uses new test library	2022-01-31 05:54:43 +00:00
David Harris	2d112698b7	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
Ross Thompson	d52c5b0393	LSU and IFU cleanup.	2022-01-28 15:26:06 -06:00
Ross Thompson	de0bef4f5b	Updated wave.do to match the ifu/lsu changes.	2022-01-28 14:37:15 -06:00
Ross Thompson	147d71fd46	Clean up of mmu instances in IFU and LSU.	2022-01-28 14:02:05 -06:00
Ross Thompson	4a8d0cb981	Moved spills to own module.	2022-01-28 13:40:35 -06:00
Ross Thompson	7fedc6b878	Cleaned up the InstrMisalignedFault.	2022-01-28 13:19:24 -06:00
Ross Thompson	1bb8d36308	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
Ross Thompson	d7d7c1cb7d	Relocated the misalignment faults.	2022-01-27 16:03:00 -06:00
David Harris	87aa0724a2	IFU cleanup	2022-01-27 17:18:55 +00:00
David Harris	218ff3e25d	IFU cleanup	2022-01-27 16:41:57 +00:00
David Harris	1c22077841	Optimized out second adder from IFU for PC+2	2022-01-27 16:06:24 +00:00
David Harris	62e5c7fd13	Comments in LSU code about restructuring	2022-01-27 15:53:59 +00:00
Ross Thompson	9a9dfcae40	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-27 08:45:33 -06:00
Ross Thompson	d38ab9d2d7	Increased number of concurrent tests.	2022-01-27 08:45:25 -06:00
David Harris	975c0e72c8	Set up rv32emc config	2022-01-27 14:37:58 +00:00
Ross Thompson	75c33bc6c9	BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush.	2022-01-27 07:59:59 -06:00
Ross Thompson	b961b104e0	Added colors to regression script to make it easy to pick out success from fail.	2022-01-26 22:40:32 -06:00
Ross Thompson	c3a78553be	Removed mux in PCNextF logic. Minor IFU improvements.	2022-01-26 22:33:26 -06:00
Ross Thompson	23c4ba2777	1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. ... 2. Removed the write address delay from simpleram.sv 3. Fixed rv32tim and rv32ic mode to handle missalignment correctly. 4. Added imperas32i and imperas32c to rv32tim mode.	2022-01-26 18:23:39 -06:00
Ross Thompson	2c982dca03	IFU simplifications.	2022-01-26 13:54:59 -06:00
David Harris	c6adb7b6b1	Updated configs to fix GPIO address to match FU540	2022-01-26 18:16:34 +00:00
David Harris	c60bb68bff	Testgen working for Lab 2	2022-01-26 18:01:51 +00:00
Ross Thompson	728e46a794	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-25 19:21:04 -06:00
David Harris	22c84dcd80	simpleram simplification	2022-01-25 19:46:13 +00:00
David Harris	8bf73d0eb3	simpleram simplification	2022-01-25 19:40:07 +00:00
David Harris	f07123ff0f	simpleram simplification	2022-01-25 18:26:31 +00:00
David Harris	7ac44cb3fc	simpleram address simplification	2022-01-25 18:17:33 +00:00
David Harris	5eb71a3bbe	simpleram address simplification	2022-01-25 18:00:50 +00:00
David Harris	d9888c91a6	simpleram clk and reset simplification	2022-01-25 17:34:15 +00:00
David Harris	5cb879129e	Start of IFU cleanup	2022-01-25 17:31:53 +00:00
Ross Thompson	4d4d9ac8cf	Added spill support back into the IROM IFU.	2022-01-21 15:50:54 -06:00