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118 Commits

Author SHA1 Message Date
Ross Thompson
fd187e9ee6 Merge branch 'main' of github.com:ross144/cvw 2023-07-24 10:47:05 -05:00
Ross Thompson
d239b0649e Improved timing constraints for arty a7 to push clock speed to 20Mhz. 2023-07-24 10:46:49 -05:00
Ross Thompson
6e17cfba03 At least it simulates and gets through fpga elaboration. 2023-07-21 18:40:26 -05:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
37078f3d9b Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Jacob Pease
36785848a5 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
7873d26678 Fixed a bunch of timing constraints for the arty a7 board. 2023-07-19 17:08:16 -05:00
Ross Thompson
4b3b590f21 Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits. 2023-06-22 12:55:49 -05:00
Ross Thompson
626a918668 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
24b8c6c391 I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. 2023-06-16 17:00:27 -05:00
Jacob Pease
2ad9c72acc The Vivado-RISC-V SDC works. Wally is now booting through it. 2023-05-26 15:42:33 -05:00
Ross Thompson
a6903ac5f3 Yeah We boot linux on the arty a7! 2023-04-19 11:17:33 -05:00
Ross Thompson
c463bd8cdd Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram. 
but the data is wrong.
 2023-04-19 10:35:18 -05:00
Ross Thompson
bb4ebd9b61 More debug stuff. 2023-04-18 16:00:10 -05:00
Ross Thompson
667524efcb Added more signals to debugger in hopes I can figure out why the mig is not responding. 2023-04-18 15:51:52 -05:00
Jacob Pease
53de2bf782 AHB triggers write, but AXI side doesn't update. 2023-04-18 15:23:22 -05:00
Ross Thompson
2df6c6cb0f It's almost working. 2023-04-18 14:24:59 -05:00
Ross Thompson
ac95087042 Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. 2023-04-17 20:05:59 -05:00
Ross Thompson
dd7f5310e4 Fixed timing constraint issue. 2023-04-17 19:53:43 -05:00
Ross Thompson
00c61fc5b3 Found the DDR3 memory is not ready when issuing the first store. 2023-04-17 19:33:13 -05:00
Ross Thompson
8bebc56b56 Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8. 2023-04-17 18:39:25 -05:00
Ross Thompson
8377ff8c51 Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way. 2023-04-17 16:37:18 -05:00
Ross Thompson
96781e0b2a Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there. 2023-04-17 16:00:02 -05:00
Ross Thompson
fad0366d26 Adding in the ILA to the arty a7. 2023-04-17 14:54:10 -05:00
Ross Thompson
5da5b76449 Fixed more issues with arty a7 constarints. 2023-04-16 13:25:02 -05:00
Ross Thompson
d2272c0620 Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
 2023-04-15 11:13:28 -05:00
Ross Thompson
c9445384d7 Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure. 2023-04-14 18:02:16 -05:00
Ross Thompson
1861ca8c86 Fixed more bugs in the ila debug constraints. 2023-04-11 14:32:53 -05:00
Ross Thompson
b015e736a0 Updated to help debut Jacob's crossbar woes. 2023-04-11 14:22:42 -05:00
Ross Thompson
c7104bebd3 Fixed sum bugs with arty a7 ila script. 2023-04-11 10:00:06 -05:00
Ross Thompson
6123efd5b2 Updates for arty a7. 2023-04-10 17:02:19 -05:00
Ross Thompson
2abd164d03 Fixed syntax errors in arty7 top level. 2023-04-10 16:08:40 -05:00
Ross Thompson
81fb076e9e Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
Ross Thompson
5aa614858f Started putting together the arty a7 board package files. 2023-04-10 13:15:55 -05:00
Jacob Pease
2b9e5608a4 Build doesn't work. AXI Crossbar has problems. 2023-04-06 16:01:58 -05:00
Ross Thompson
c8baffba7c Started constrains file for arty a7 fpga. 2023-03-24 20:38:13 -05:00
Ross Thompson
c10d98b1c8 Updated fpga constraints to remove critical warning. 2023-03-24 19:09:36 -05:00
Jacob Pease
303c997a69 Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore 2023-03-24 17:01:27 -05:00
Ross Thompson
fe163bbab3 Updated fpga ila script. 2023-03-06 13:14:48 -06:00
Jacob Pease
2822cb273c AXI Crossbar is working. Fixed address width in generator script. 2023-02-22 15:13:16 -06:00
Jacob Pease
c1e7526570 Fixed debug signal names. Builds on the fpga. Bug in the crossbar. 2023-02-16 17:33:21 -06:00
Ross Thompson
920bd40822 fpga constraints updates 2023-02-07 15:22:14 -06:00
Jacob Pease
24d0b1c860 Added extra core signal to mark_debug.txt. Modified wally.tcl 2023-01-23 17:00:24 -06:00
Ross Thompson
64eaaa670c More fixes for the debug2.xdc constraints. 2023-01-20 20:48:19 -06:00
Ross Thompson
ee4c78c7fa More fixes to fpga ila debugger. 2023-01-20 20:28:21 -06:00
Ross Thompson
3effeb42c3 Fixed fpga constraints. 2023-01-20 20:18:04 -06:00
Ross Thompson
442de3f5b7 Updated fpga constraints. 2023-01-20 20:16:33 -06:00
Ross Thompson
e06237ad92 Removed mark_debug vivado directive from source code. 
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
 2023-01-20 19:43:18 -06:00
Ross Thompson
9d8fed1d35 Test commit. 2023-01-20 17:27:09 -06:00
Ross Thompson
b25b93df11 Repaired fpga debugger. 2023-01-20 15:26:52 -06:00