Ross Thompson
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0257c08641
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Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
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2021-12-19 14:00:30 -06:00 |
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Ross Thompson
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e43aa6ead4
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Merge branch 'main' into fpga
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2021-11-29 10:06:53 -06:00 |
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David Harris
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6ae9aa7d80
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lint cleanup: FPU and privileged
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2021-10-23 09:41:24 -07:00 |
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Ross Thompson
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99070127d8
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Added debugging directives to system verilog.
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2021-09-27 13:57:46 -05:00 |
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David Harris
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654f3d1940
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Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
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2021-09-13 12:40:40 -04:00 |
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bbracker
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5e9a39e755
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fixed bug where M mode was sensitive to S mode traps
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2021-09-07 19:14:39 -04:00 |
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Ross Thompson
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4f3f26c5cb
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Switched ExceptionM to dcache to be just exceptions.
Added test bench logic to hold forces until the W stage is unstalled.
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2021-08-13 15:53:50 -05:00 |
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David Harris
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e3bf8db80b
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trap.sv comment cleanup
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2021-07-17 16:01:07 -04:00 |
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David Harris
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b2c2194478
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trap.sv cleanup
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2021-07-17 15:57:10 -04:00 |
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David Harris
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348e69c096
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hptw: Removed NonBusTrapM from LSU
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2021-07-17 15:24:26 -04:00 |
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David Harris
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49ec45d04d
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hptw: Removed NonBusTrapM from LSU
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2021-07-17 15:22:24 -04:00 |
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Ross Thompson
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e17de4eb11
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Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
This solves the committedM issue.
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2021-07-14 15:00:33 -05:00 |
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Ross Thompson
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d85bf23af3
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Merged several of the load/store/instruction access faults inside the mmu.
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
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2021-07-06 13:43:53 -05:00 |
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bbracker
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7a652139b5
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mcause test fixes and s-mode interrupt bugfix
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2021-06-16 17:37:08 -04:00 |
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David Harris
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9dd3857c26
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Fixed lint WIDTH errors
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2021-06-09 20:58:20 -04:00 |
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bbracker
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5026a42fac
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* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
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2021-06-08 12:32:46 -04:00 |
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bbracker
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28abd28b1f
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fixed InstrValid signals and implemented less costly MEPC loading
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2021-06-02 10:03:19 -04:00 |
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Domenico Ottolia
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830787e3e1
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Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
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2021-04-29 20:42:14 -04:00 |
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ushakya22
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de23edcfb9
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fix to pcm bug
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2021-04-29 15:21:08 -04:00 |
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Thomas Fleming
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5bff582608
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Write PCM to TVAL registers
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2021-04-22 16:17:57 -04:00 |
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Domenico Ottolia
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b1cd107a00
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Add tests for scause and ucause
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2021-04-15 19:41:25 -04:00 |
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Domenico Ottolia
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a149f2f3d8
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Add support for vectored interrupts
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2021-04-15 19:13:42 -04:00 |
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bbracker
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ccff1e6c99
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rv64 interrupt servicing
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2021-04-14 10:19:42 -04:00 |
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David Harris
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429f48e766
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Rename ifu/dmem/ebu signals to match uarch diagram
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2021-02-02 15:09:24 -05:00 |
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David Harris
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92bf1674b4
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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07af481b67
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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