65 Commits

Author	SHA1	Message	Date
Noah Boorstin	fa1407f6e3	everyone gets a bootram	2021-03-18 12:35:37 -04:00
Shreya Sanghai	d9b1e7d67f	added gshare and global history predictor	2021-03-16 17:03:01 -04:00
Shreya Sanghai	a79e26f9d8	added global history branch predictor	2021-03-16 16:06:40 -04:00
Shreya Sanghai	518618ad38	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Ross Thompson	8e51935082	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Thomas Fleming	e57b6cf18c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-03-11 00:15:58 -05:00
Ross Thompson	9a93193d6a	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
Thomas Fleming	85dcbee86b	Place tlb parameters into constant header file	2021-03-05 13:35:24 -05:00
Shreya Sanghai	7cd8f1a592	added performance counters	2021-03-04 11:42:52 -05:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	9511dcac84	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	9530039e3d	Implemented adrdec for uncore	2021-01-29 17:28:53 -05:00
David Harris	d104e5a4be	Moving data memory to uncore	2021-01-29 15:37:51 -05:00
David Harris	b7988e536f	Reset Vector moved to config file	2021-01-25 15:57:36 -05:00
David Harris	bf07ec92b5	Added test configurations	2021-01-25 11:28:43 -05:00