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57 Commits

Author SHA1 Message Date
Kip Macsai-Goren
ffae1c5ee6 added fs=00 to status fp enabled test 2022-12-22 15:15:53 -08:00
Kip Macsai-Goren
a768d70093 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Kip Macsai-Goren
1d268fded4 added corrrect scr read out of uart to periph test 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
badc684f07 added copies of 64 bit tests to 32 bit periph and priv tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
282d06b45f added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
d4dd2dcc08 Added test for UART FIFO timeout. Does not pass regression 2022-10-25 05:35:56 +00:00
Kip Macsai-Goren
0d2fcaeab1 added xlen and endianness test edits. xlen passes but endinanness still won't make 2022-09-26 05:03:19 +00:00
Kip Macsai-Goren
dda3b2d383 ported endianness tests to 32 bits (not tested in regression yet) 2022-09-18 00:10:29 +00:00
David Harris
8b8f045491 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
e3ea86f984 Started plic-s tests 2022-08-03 03:48:08 +00:00
David Harris
d2de84a456 Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
763a6d7340 Fixed UART reference output 2022-07-27 22:16:38 +00:00
David Harris
f61f0645fe Finished UART test 2022-07-27 04:06:59 +00:00
slmnemo
a32698811d Updated reference file for UART test 2022-07-26 09:39:31 -07:00
slmnemo
5b71ceac5c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
0bfc3fda1b Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
e02c67ed5e fixed 32priv tests, now passing 2022-07-22 15:35:20 -07:00
Daniel Torres
d95b266d49 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
slmnemo
840c40a7ab UART updates and PMA fix 2022-07-22 14:49:03 -07:00
slmnemo
6d8988f71f Added test comments to reference output 2022-07-22 12:35:59 -07:00
Daniel Torres
5d7171f6f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
526f70e772 commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
slmnemo
12c92a05ff Added new PLIC and UART tests 2022-07-22 07:12:55 -07:00
slmnemo
b3cd9de9e8 Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests. 2022-07-05 18:21:17 -07:00
slmnemo
448c9fdbb9 Add CLINT tests from book 2022-06-27 20:09:58 -07:00
slmnemo
ddf757078b Added reset read testcodes to GPIO 2022-06-27 18:56:35 -07:00
slmnemo
4c8f5fbd89 Fixed error in GPIO signature 2022-06-23 14:12:28 -07:00
David Harris
66b148b76e GPIO tests 2022-06-23 21:06:11 +00:00
slmnemo
3d794742e9 Updating new GPIO tests 2022-06-23 13:22:00 -07:00
slmnemo
2b2ddbcc5e Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Kip Macsai-Goren
94cb6caec6 Fixed priv test reference outputs to have the right number of "DEADBEEF"s (1024) 2022-05-12 22:30:14 +00:00
David Harris
9b7aab122e wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
Kip Macsai-Goren
7249879a74 clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals 2022-05-04 23:01:23 +00:00
Kip Macsai-Goren
a9a434fced removed fp-diabled test and leftover mimpid test 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
f36fdf940d removed instruction misaligned tests from trap tests, signatures 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
badbe0840f renamed all tests to have lower-case titles except for WALLY 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
64ba550493 general test cleanup of comments and old files 2022-04-29 19:55:29 +00:00
Kip Macsai-Goren
36f5624255 re-renamed status-mie-s to status-sie 2022-04-29 19:55:13 +00:00
Kip Macsai-Goren
75e90f193e added missing SIE test 2022-04-29 19:54:29 +00:00
Kip Macsai-Goren
c0b56bfd27 renamed PIE-stack tests to status-mie for clarity 2022-04-29 18:30:39 +00:00
Kip Macsai-Goren
2f17edb5f4 added missing output for sret 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
aedf0341af added 32 bit versions of new tests. all but timeout wait pass regression 2022-04-28 18:14:07 +00:00
Kip Macsai-Goren
fe14b9f188 Added 32 bit privilege tests that work but for one bug 2022-04-20 17:32:29 +00:00
Kip Macsai-Goren
7ed0c7b8b6 Updated 32 bit PMA tests to reflect new clint rules 2022-04-20 17:31:08 +00:00
Kip Macsai-Goren
7412979b71 added unfinished tests to 32 bit library 2022-04-02 19:15:07 +00:00
bbracker
1bb73dad7d change main.config so that buildroot expects linux.config and busybox.config to be at $RISCV/buildroot 2022-03-02 17:46:33 +00:00
Kip Macsai-Goren
f14acac1bf Changed PMA tests to only allow native length accesses to CLINT 2022-02-28 19:22:44 +00:00
Kip Macsai-Goren
369e799ce3 added minor sections to MMU tests that had been missing, global bits still need to be checked 2022-02-27 23:28:44 +00:00
Kip Macsai-Goren
04892c5d38 added scratch register tests for 64 and 32 bits 2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
dcb5d0f6a9 Added misa test for both 32 and 64 bits 2022-02-18 19:41:50 +00:00