bbracker
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f4f3ef0307
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linux testbench progress
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2021-07-18 18:47:40 -04:00 |
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Katherine Parry
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3527620c0b
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fdivsqrt inegrated, but not completley working
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2021-07-18 14:03:37 -04:00 |
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Ross Thompson
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a0017e39e2
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Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.
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2021-07-17 21:02:24 -05:00 |
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David Harris
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c29a2ff8df
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Started atomics
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2021-07-17 21:11:41 -04:00 |
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bbracker
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6feb95c779
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swapped out linux testbench signal names
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2021-07-17 14:48:12 -04:00 |
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David Harris
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9741b01465
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hptw: minor cleanup
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2021-07-17 13:40:12 -04:00 |
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David Harris
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37cc2ca30f
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hptw: factored pregen
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2021-07-17 11:11:10 -04:00 |
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David Harris
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622a14cbdd
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Removed more unused signals from ahblite
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2021-07-17 02:21:54 -04:00 |
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Kip Macsai-Goren
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3d14d573a0
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included virtual memory tests in testbench
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2021-07-16 17:57:24 -04:00 |
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Ross Thompson
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965f34d78f
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Added guide for Ben to do linux conversion.
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2021-07-16 15:04:30 -05:00 |
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Ross Thompson
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abce241f68
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Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
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2021-07-16 14:21:09 -05:00 |
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Ross Thompson
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96aa106852
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Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
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2021-07-15 11:56:35 -05:00 |
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Ross Thompson
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4549a9f1c9
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Merge branch 'main' into dcache
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2021-07-15 11:55:20 -05:00 |
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Ross Thompson
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c39a228266
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Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
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2021-07-15 11:00:42 -05:00 |
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Ross Thompson
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f234875779
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dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
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2021-07-14 23:08:07 -05:00 |
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Ross Thompson
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6163629204
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Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
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2021-07-14 22:26:07 -05:00 |
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Katherine Parry
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701ea38964
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Fixed lint warning
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2021-07-14 21:24:48 -04:00 |
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Ross Thompson
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d3a1a2c90a
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Fixed d cache not honoring StallW for uncache writes and reads.
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2021-07-14 17:23:28 -05:00 |
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Ross Thompson
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771c7ff130
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Routed CommittedM and PendingInterruptM through the lsu arb.
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2021-07-14 16:18:09 -05:00 |
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Ross Thompson
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278bbfbe3c
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Partially working changes to support uncached memory access. Not sure what CommitedM is.
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2021-07-13 17:24:59 -05:00 |
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Katherine Parry
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acdd2e4504
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Fixed writting MStatus FS bits
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2021-07-13 13:20:30 -04:00 |
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Ross Thompson
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d3ffbe0e5d
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Modularized the shadow memory to reduce performance hit.
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2021-07-13 10:55:57 -05:00 |
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Ross Thompson
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17dc488010
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Got the shadow ram cache flush working.
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2021-07-13 10:03:47 -05:00 |
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Ross Thompson
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9fe6190763
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Team work on solving the dcache data inconsistency problem.
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2021-07-12 23:46:32 -05:00 |
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Ross Thompson
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6b42b93886
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Now updates the dtim with the dirty data in the dcache.
Simulation is showing issues. It lookslike the cache is not
evicting the correct data.
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2021-07-12 15:13:27 -05:00 |
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Ross Thompson
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8ca8b9075d
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Progress towards the test bench flush.
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2021-07-12 14:22:13 -05:00 |
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Katherine Parry
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0cc07fda1b
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Almost all convert instructions pass Imperas tests
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2021-07-11 18:06:33 -04:00 |
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bbracker
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0e708a72f3
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more completely uncomment MMU tests to make sim wally work
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2021-07-06 14:33:52 -04:00 |
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Kip Macsai-Goren
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770420b448
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added new mmu tests to makefrag and commented out in the testbench
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2021-07-05 10:54:30 -04:00 |
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David Harris
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e65fb5bb35
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Added F_SUPPORTED flag to disable floating point unit when not in MISA
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2021-07-05 10:30:46 -04:00 |
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David Harris
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c897bef8cd
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Ben Bracker
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9709bd78e1
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stop busybear from hanging
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2021-07-02 17:22:09 -05:00 |
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bbracker
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9927f771cc
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linux testbench now ignores HWRITE glitches caused by flush glitches
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2021-06-25 09:28:52 -04:00 |
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bbracker
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2694a7a43f
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made testbench-linux's PCDwrong be FlushD
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2021-06-25 08:15:19 -04:00 |
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Katherine Parry
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bc8d660bc5
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FPU forwarding reworked pt.1
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2021-06-24 18:39:18 -04:00 |
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bbracker
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55cf205222
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-24 01:42:41 -04:00 |
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bbracker
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b84419ff4e
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overhauled linux testbench and spoofed MTTIME interrupt
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2021-06-24 01:42:35 -04:00 |
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Katherine Parry
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44af47608c
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fpu clean-up
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2021-06-23 16:42:40 -04:00 |
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Katherine Parry
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9eb6eb40bf
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rv64f FLW passes imperas tests
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2021-06-22 16:36:16 -04:00 |
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David Harris
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82515862e3
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Commented out 100k tests to improve speed
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2021-06-21 01:43:18 -04:00 |
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David Harris
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aef408af58
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Reversed [0:...] with [...:0] in bus widths across the project
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2021-06-21 01:17:08 -04:00 |
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bbracker
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5afad80432
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-20 22:29:40 -04:00 |
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bbracker
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665a67f442
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linux actually uses FPU now!
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2021-06-20 22:29:21 -04:00 |
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Katherine Parry
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26bad083ad
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all rv64f instructions except convert, divide, square root, and FLD pass
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2021-06-20 20:24:09 -04:00 |
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bbracker
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1f2a967e0f
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read from MSTATUS workaround because QEMU has incorrect MSTATUS
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2021-06-20 10:11:39 -04:00 |
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bbracker
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2611d214a6
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testbench update b/c QEMU extends 32b CSRs to 64b
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2021-06-20 09:24:19 -04:00 |
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bbracker
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9469367da3
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make buildroot ignore SSTATUS because QEMU did not originally log it
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2021-06-20 05:31:24 -04:00 |
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bbracker
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78f4703dc9
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MSTATUS workaround
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2021-06-20 04:48:09 -04:00 |
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bbracker
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927d99cf3b
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workaround for ignoring MTIME
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2021-06-20 02:26:39 -04:00 |
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bbracker
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3e32ba3684
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make buildroot waves only turn on after a user-specified point
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2021-06-20 00:39:30 -04:00 |
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