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149 Commits

Author SHA1 Message Date
David Harris
1569bfbb98 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Kevin Thomas
c4a9bb4269 Formating white space 2023-04-05 15:30:55 -05:00
Kevin Thomas
5e5842893b Minor change with the IFU in the decompress module, in the compressed instruction truth table. 
The truth table is already fully covered, removed redundant last case checking
 2023-04-05 10:27:52 -05:00
Sydney Riley
440e41bb3e expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions. 2023-04-02 23:51:34 -07:00
Ross Thompson
69f6b291c6 Possible fix for issue 148. 
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.

I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.

This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
 2023-03-28 14:47:08 -05:00
Ross Thompson
730f3ac84e Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
David Harris
c4c7f5378e Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault 2023-03-22 06:29:30 -07:00
David Harris
77fb1b57f4 Fix Issue 145 2023-03-22 04:33:14 -07:00
Ross Thompson
a27051b8a8 Updated NextAdr to NextSet. 2023-03-13 14:54:13 -05:00
Ross Thompson
ede9d49ce4 Changes BTA to BPBTA. 2023-03-12 14:36:46 -05:00
Ross Thompson
e233b63752 Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10. 2023-03-12 13:21:22 -05:00
Ross Thompson
4b539de184 Renamed signals to be consistent with textbook. 2023-03-06 18:29:31 -06:00
Ross Thompson
6fc157e628 Renamed PCFSpill to PCSpillF. 2023-03-06 17:50:57 -06:00
Ross Thompson
e831efddaf Renamed InstrFirstHalf to InstrFirstHalfF. 2023-03-06 17:48:57 -06:00
Ross Thompson
7dd8fa16c1 Renamed BTB misprediction to BTA. 2023-03-03 00:18:34 -06:00
Ross Thompson
4b501f6e03 Added the i and d cache cycle counters. 2023-03-02 23:54:56 -06:00
Ross Thompson
3d1ffac7d7 Cleaned up branch predictor performance counters. 2023-03-01 17:05:42 -06:00
Ross Thompson
a61f8bc4cf Set bp to use instruction class prediction by default. 2023-03-01 11:52:42 -06:00
Ross Thompson
e8744684cd Branch predictor cleanup. 
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
 2023-03-01 11:24:24 -06:00
Ross Thompson
08a1153ae9 More btb cleanup. 2023-03-01 10:47:00 -06:00
Ross Thompson
dd2433f7ff Minor fix to btb. 2023-03-01 10:45:40 -06:00
Ross Thompson
2773048bd4 Name cleanup. 2023-02-28 17:48:58 -06:00
Ross Thompson
87013ccaf0 Found the performance bug with the branch predictor btb power saving update. 2023-02-28 15:57:34 -06:00
Ross Thompson
8af61c0cc0 Name changes to reflect diagrams. 2023-02-28 15:37:25 -06:00
Ross Thompson
a823d8d021 Undid the btb update as it reduces performance. 2023-02-28 15:21:56 -06:00
Ross Thompson
3261f31e88 This icpred and btb changes are causing a performance issue. 2023-02-27 20:00:50 -06:00
Ross Thompson
69e8358639 Modified the BTB to save power by not updating when the prediction is unchanged. 2023-02-27 17:37:29 -06:00
Ross Thompson
44361f0a34 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-27 09:48:03 -06:00
Ross Thompson
a81cc883e9 Signal name changes. 2023-02-27 00:39:19 -06:00
Ross Thompson
447f6b1443 Branch predictor cleanup. 2023-02-26 21:28:36 -06:00
Ross Thompson
3804626166 Create module for instruction class prediction and decoding. 2023-02-26 20:20:30 -06:00
David Harris
d2fd34efe6 Renamed DAPageFault to UpdateDA 2023-02-26 17:51:45 -08:00
Ross Thompson
bb276da6eb Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-02-26 12:06:06 -06:00
David Harris
4579a9d0c2 Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED 2023-02-26 09:38:32 -08:00
Ross Thompson
7500bb75c6 PHT was enabled using the wrong ~flush and ~stall. 2023-02-24 22:57:32 -06:00
Ross Thompson
63b9f9ca3d gshare cleanup. 2023-02-24 22:55:51 -06:00
Ross Thompson
ed7ab402ad More signal renames. 2023-02-24 19:56:55 -06:00
Ross Thompson
e549bec060 Renamed signals to match new figures. 2023-02-24 19:51:47 -06:00
Ross Thompson
6ff524d843 Renamed signals to match figure 10.18. 2023-02-24 19:22:14 -06:00
Ross Thompson
4058a49985 Possible fix to btb performance issue. 2023-02-24 18:36:41 -06:00
Ross Thompson
5c52827f51 Cleanup. 2023-02-24 18:20:42 -06:00
Ross Thompson
d030d323fd Completed critical path gshare fix. 2023-02-24 18:02:00 -06:00
Ross Thompson
c2021927ce Prep to fix gshare critical path. 2023-02-24 17:54:48 -06:00
Ross Thompson
4ffaa75c2a Modified btb forwarding logic to reduce critical path. 2023-02-24 17:47:43 -06:00
Ross Thompson
6e8791a0a5 Major cleanup of bp. 2023-02-23 16:19:03 -06:00
Ross Thompson
d880720b7e Partial replacement of InstrClassX with {JalX, RetX, JumpX, and BranchX}. 2023-02-23 15:55:34 -06:00
Ross Thompson
500764f97b Branch predictor cleanup. 2023-02-23 15:15:14 -06:00
Ross Thompson
70f7f59332 Moved more branch predictor logic into the performance counter block. 2023-02-23 15:14:56 -06:00
Ross Thompson
195343c84f Added if generate around bp logic only used with performance counters. 2023-02-23 14:39:31 -06:00
Ross Thompson
ed91fc5ce3 Renamed PCPredX to BTAX. 2023-02-23 14:33:32 -06:00
Ross Thompson
1af7b8051e Fixed bug in basic gshare. 2023-02-22 12:54:46 -06:00
Ross Thompson
fd5b940839 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-22 09:11:57 -06:00
Ross Thompson
5ecbc830cf Oups. Turns out dc_shell does not like string parameters. 
Switched gshare to use an integer parameter to select between gshare and global.
 2023-02-22 09:11:46 -06:00
David Harris
bc4410e686 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-21 09:58:18 -08:00
David Harris
0b9fd8a4b3 Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well. 2023-02-21 09:32:17 -08:00
Ross Thompson
fd5c12431e Fixed typo in the global branch predictor. 2023-02-20 18:48:02 -06:00
Ross Thompson
d2e06d9ef0 Cleanup branch predictor files. 2023-02-20 18:45:45 -06:00
Ross Thompson
a14c71bd95 Renamed branch predictors and consolidated global and gshare predictors. 2023-02-20 18:42:37 -06:00
Ross Thompson
68e39eeb66 Fixed another bug in the btb. 2023-02-20 17:54:22 -06:00
Ross Thompson
5187c78184 Fixed forwarding bug in the BTB. 2023-02-20 17:03:45 -06:00
Ross Thompson
1982c66b72 Simiplified BTB. 2023-02-20 15:39:42 -06:00
David Harris
081a817925
Merge pull request #98 from ross144/main 
New gshare implementation
 2023-02-20 11:27:47 -08:00
David Harris
a59526fc8e Fixed IROM size parameters 2023-02-20 05:32:43 -08:00
David Harris
1d3b41e0fb New expression for BTB_SIZE to avoid error during sky90 synthesis 2023-02-20 04:02:00 -08:00
Ross Thompson
2d417c33a4 Simplified BTB by removing the valid bit. the instruction class provides the equivalent information. 2023-02-19 23:53:20 -06:00
Ross Thompson
0d79c0cebe Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-19 22:54:27 -06:00
Ross Thompson
b32093b33b Simplified branch predictor. 2023-02-19 22:49:48 -06:00
David Harris
0ac9c9e62a Added BTB_SIZE parameter independent of BPRED_SIIZE 2023-02-19 20:13:50 -08:00
David Harris
5b197f4f9d Parameterized btb to depend on BPRED_SIZE 2023-02-19 19:59:07 -08:00
Ross Thompson
9ee48637dc Possibly much better branch predictor implemention. 
The complexity is significantly reduced.
 2023-02-19 00:17:37 -06:00
Ross Thompson
d44cb1febb Minor fix. 2023-02-18 23:55:46 -06:00
David Harris
0eda753dc4 Removed unused PredInstrClassE register from bpred 2023-02-18 05:59:25 -08:00
Ross Thompson
0cacfbd322 Renamed globalhistory predictor. 2023-02-17 16:08:34 -06:00
Ross Thompson
2f1bebfd57 Fixed global history predictor. 2023-02-17 16:05:48 -06:00
Ross Thompson
a95be0b567 More updates. 2023-02-17 15:53:49 -06:00
Ross Thompson
df4a27a2e3 Updated global history predictor. 2023-02-17 15:53:15 -06:00
Ross Thompson
0d271130b9 Fixed a branch predictor performance issue. 2023-02-17 15:37:03 -06:00
Ross Thompson
a325adf1be Fixed bug with branch predictor. 2023-02-17 10:57:50 -06:00
Ross Thompson
094b307724 Merge branch 'main' of github.com:ross144/cvw 2023-02-13 18:54:07 -06:00
Ross Thompson
9c9acc0055 Updated gshare (no speculation) to have better performance. 2023-02-13 18:52:52 -06:00
Ross Thompson
33d2bf84f8 More fixeds to global history. 2023-02-13 18:08:51 -06:00
Ross Thompson
a579bbcdd1 Fixed global history predictor. 2023-02-13 18:08:13 -06:00
Ross Thompson
bbc6095260 Updated global history predictor. 2023-02-13 18:07:32 -06:00
Ross Thompson
9f25b53b36 Fixed bug in basic gshare implementation. Should be a better comparison to the speculative versions now. 2023-02-13 17:57:05 -06:00
Ross Thompson
b298a8afc5 Created copy of gshare. I think there may be a simpler implementation. 2023-02-13 17:29:51 -06:00
Ross Thompson
a80dbd3aec Further branch predictor improvements. 2023-02-13 17:23:56 -06:00
Ross Thompson
717cba270c Partial improvement. 2023-02-13 17:10:24 -06:00
Ross Thompson
f4af38a004 Hacked commit. Fixes the gshare bugs introduced last week. 
Need to recover the good changes in the next commit.
 2023-02-13 16:14:17 -06:00
Ross Thompson
1d74663f42 Partial fix for gshare bugs from the last two weeks. 2023-02-13 11:57:25 -06:00
Ross Thompson
58749a8c57 Removed another bit from btb class. 2023-02-12 11:33:43 -06:00
Ross Thompson
1e0667db1d More simplifications to the BP. 2023-02-10 17:09:35 -06:00
Ross Thompson
9c4da7381f Experimental branch prediction optimization. 2023-02-10 15:45:56 -06:00
Ross Thompson
c229f0064e Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic. 2023-02-10 10:33:10 -06:00
Ross Thompson
282ffd1313 RAS and RAS documentation now consistent. 2023-02-10 09:06:51 -06:00
Ross Thompson
faf7cd8c8a Updated globalhistory predictor. 2023-02-09 14:48:02 -06:00
Ross Thompson
996bb289d3 Simplified branch predictor. 2023-02-08 18:24:38 -06:00
Ross Thompson
7263fab4b1 Branch predictor cleanup. 2023-02-07 14:01:59 -06:00
David Harris
b13087e706 Fixed merge issues on synthDC PR 2023-02-04 04:13:40 -08:00
David Harris
99d179dd3e Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00