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Updated gshare (no speculation) to have better performance.

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This commit is contained in:
Ross Thompson 2023-02-13 18:52:52 -06:00
parent b298a8afc5
commit 9c9acc0055
3 changed files with 11 additions and 90 deletions
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4
src/ifu/bpred/bpred.sv
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@ -110,8 +110,8 @@ module bpred (
.PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
.PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor

17
src/ifu/bpred/gshare.sv
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@ -31,12 +31,12 @@
module gshare #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCE,
input logic [`XLEN-1:0] PCNextF, PCM,
input logic BranchInstrE, BranchInstrM, PCSrcE
);
@ -44,20 +44,20 @@ module gshare #(parameter k = 10) (
logic [1:0] DirPredictionD, DirPredictionE;
logic [1:0] NewDirPredictionE, NewDirPredictionM;
logic [k-1:0] GHRF, GHRD, GHRE, GHR;
logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR;
logic [k-1:0] GHRNext;
logic PCSrcM;
assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
.ce1(~StallF), .ce2(~StallM & ~FlushM),
.ra1(IndexNextF),
.rd1(DirPredictionF),
.wa2(IndexE),
.wd2(NewDirPredictionE),
.we2(BranchInstrE & ~StallM & ~FlushM),
.wd2(NewDirPredictionM),
.we2(BranchInstrM & ~StallW & ~FlushW),
.bwe2(1'b1));
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
@ -75,6 +75,7 @@ module gshare #(parameter k = 10) (
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
endmodule

80
src/ifu/bpred/gshare_copy.sv
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@ -1,80 +0,0 @@
///////////////////////////////////////////
// globalHistoryPredictor.sv
//
// Written: Shreya Sanghai
// Email: ssanghai@hmc.edu
// Created: March 16, 2021
// Modified:
//
// Purpose: Global History Branch predictor with parameterized global history register
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module gshare_copy #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,
output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE,
// update
input logic [`XLEN-1:0] PCNextF, PCE,
input logic BranchInstrE, BranchInstrM, PCSrcE
);
logic [k-1:0] IndexNextF, IndexE;
logic [1:0] DirPredictionD, DirPredictionE;
logic [1:0] NewDirPredictionE, NewDirPredictionM;
logic [k-1:0] GHRF, GHRD, GHRE, GHR;
logic [k-1:0] GHRNext;
logic PCSrcM;
assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
.ce1(~StallF), .ce2(~StallM & ~FlushM),
.ra1(IndexNextF),
.rd1(DirPredictionF),
.wa2(IndexE),
.wd2(NewDirPredictionE),
.we2(BranchInstrE & ~StallM & ~FlushM),
.bwe2(1'b1));
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, DirPredictionD, DirPredictionE);
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
endmodule