Ross Thompson
4a61d1b4f1
Fixed issue #412
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The root cause was DTLB miss leads to page fault exception with concurrent I$ miss. The HPTW hits all entries in the D$ and quickly faults. However the I$ is still waiting on the main memory.
The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.
The simplest solution is to use CommittedF to delay Exceptions like with Interrupts. Note this cannot happen with CommittedM. If the ITLB misses and the D$ also need to fetch a from the bus an ITLB page fault exception will not trigger the trap until a few stages later.
2023-10-09 16:03:37 -05:00
David Harris
d80cb36778
Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
2023-10-04 12:28:12 -07:00
David Harris
42157eaf94
UpdateDA cleanup: don't assert UpdateDA when there is no SVADU
2023-10-04 09:57:13 -07:00
David Harris
df7f2679d7
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
Ross Thompson
1a003019d6
Actually fixed non-power of 2 issue with RAS.
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Added RAS swapping to branch predictor scripts and configurations.
2023-09-27 12:25:05 -05:00
Ross Thompson
9ec2bfd052
Fixed sutble RAS bug when the stack size was not a power of 2.
2023-09-27 12:00:47 -05:00
Ross Thompson
a910425adf
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-09-14 10:16:54 -05:00
Ross Thompson
7c89154a7f
Slight modification to cachefsm.
2023-09-05 14:07:58 -05:00
Ross Thompson
f00df8d121
Merge pull request #407 from davidharrishmc/dev
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initial spill logic improvement
2023-09-05 13:29:37 -05:00
Ross Thompson
e39fc44efd
Merge pull request #406 from magpyed/cachesim_fix
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Properly gate LRUWriteEn with ~FlushStage
2023-09-05 11:10:58 -05:00
David Harris
6ab71ffca6
initial spill logic improvement
2023-09-03 04:21:13 -07:00
David Harris
1ced158596
tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
2023-09-02 12:56:36 -07:00
Limnanthes Serafini
b334e4ff1f
Properly gate LRUWriteEn with ~FlushStage
2023-09-01 23:31:02 -07:00
David Harris
98fa3a78dd
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
Kevin Kim
e4ed61a2ce
Merge branch 'openhwgroup:main' into synth_wrapper_gen
2023-08-28 09:03:10 -07:00
Kevin Kim
fc25afb3cb
make synth integerates wrapper generation and runs synth on wrapper
2023-08-28 09:02:56 -07:00
Ross Thompson
e7becd53d7
Merge pull request #398 from davidharrishmc/dev
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Completed basic tests of svnapot and svpbmt
2023-08-28 09:10:20 -05:00
David Harris
10549b7787
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
Kevin Kim
9217e1e767
synth works
2023-08-26 21:11:21 -07:00
David Harris
75986d6641
Fixed merge conflict for ZICBOP
2023-08-25 18:41:57 -07:00
David Harris
3721f8347d
Preparing to merge with CBO* changes
2023-08-25 18:41:03 -07:00
David Harris
c07ad03f9d
Initial implementation of SVNAPOT and SVPBMT does not break regression
2023-08-25 18:33:08 -07:00
David Harris
9f44241d0f
Added N and PBMT bits to MMU PTE
2023-08-24 19:44:46 -07:00
David Harris
847c0dd099
Merge pull request #393 from ross144/main
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Implemented and tested CBOZ instruction
2023-08-24 19:17:38 -07:00
David Harris
d12be1faac
Merge pull request #394 from harshinisrinath1001/main
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Improved testing of csri with priv.S!
2023-08-24 19:16:50 -07:00
harshinisrinath
49014e61bc
Improved testing of csri with priv.S
2023-08-24 18:39:15 -07:00
Ross Thompson
284ff0ab0b
Fixed minor performance bug with CBOZ.
2023-08-24 17:08:20 -05:00
Ross Thompson
fbcf6be06d
Now have CBOZ instructions working!
2023-08-24 16:47:35 -05:00
David Harris
aad722ffb1
Check for legal SATP mode values
2023-08-24 05:18:04 -07:00
Ross Thompson
e8bc339638
Oups there was a bug in the SATP fix. RV32GC was broken by the changes.
2023-08-23 09:42:46 -05:00
Ross Thompson
d9a001e87a
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-08-23 09:15:13 -05:00
Jacob Pease
0f29587b0b
Prevented writes to SATP enabling SV57. This follows the spec more accurately. Linux can now successfully probe SATP.
2023-08-22 16:25:56 -05:00
Ross Thompson
a899be7deb
Fixed bug with the cbo.inval clearing already cleared lines.
2023-08-21 17:51:51 -05:00
Ross Thompson
6337aab757
Fixed issue when with flush miss.
2023-08-18 16:36:13 -05:00
Ross Thompson
e3bb0d2820
Now we have invalidate, clean, and flush working.
2023-08-18 16:32:22 -05:00
Ross Thompson
b9af790b81
Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.
2023-08-18 15:59:39 -05:00
Ross Thompson
b842fdb863
Might have working cbo clean and flush instructions.
2023-08-18 14:48:21 -05:00
Ross Thompson
8c7eafffad
Fixed cbo instruction decode.
2023-08-18 11:32:30 -05:00
Ross Thompson
a14966e516
Updated the hazard logic for CMO operations.
2023-08-17 17:58:49 -05:00
Ross Thompson
bfde4d2c78
Found first bug in CMO implementation.
2023-08-17 16:57:54 -05:00
Ross Thompson
6a8a82d9e8
CMOZ now implemented in the D cache.
2023-08-17 12:46:40 -05:00
Ross Thompson
e74e4f3a60
Added clean and flush to cache fsm.
2023-08-16 14:23:56 -05:00
Ross Thompson
b5ca41fd2a
More progress towards cmo.
2023-08-15 18:17:15 -05:00
Ross Thompson
6284773733
The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush.
2023-08-14 16:39:18 -05:00
Ross Thompson
f678133d19
Initial CMO implementation. Just adds control signals into the L1 caches.
2023-08-14 15:43:12 -05:00
Ross Thompson
3e66653f37
Cache cleanup.
2023-07-31 14:12:53 -05:00
Ross Thompson
141e90d425
Merge pull request #372 from davidharrishmc/dev
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PLIC part select warnings fixed
2023-07-31 11:28:28 -04:00
David Harris
55d4f28efe
Merge pull request #373 from harshinisrinath1001/main
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Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing
2023-07-30 22:46:44 -07:00
Harshini Srinath
01fc7c5284
Fixed formatting
2023-07-30 18:36:25 -07:00
Harshini Srinath
811e2fd94c
Fixed formatting
2023-07-30 18:30:23 -07:00
