David Harris
2f4074b9c2
Improved RAS predictor coverage by eliminating unreachable StallM term
2023-04-07 21:37:12 -07:00
Ross Thompson
cfab7c8b45
Merge pull request #219 from davidharrishmc/dev
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Spill logic coverage and fdivsqrt cleanup
2023-04-07 23:30:52 -05:00
David Harris
5cdd3d57c7
Commented WFI non-flush in writeback stage of hazard unit
2023-04-07 21:27:13 -07:00
David Harris
b27199e276
Added vm64check tests to cover IMMU vm64
2023-04-07 21:14:52 -07:00
David Harris
0d2de13990
Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf
2023-04-07 21:11:01 -07:00
David Harris
bf9db11a57
Fixed priv.S to initialize stimecmp and agree with ImperasDV
2023-04-07 20:44:01 -07:00
David Harris
9394389fec
Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed
2023-04-07 20:43:28 -07:00
David Harris
16eca598ba
Fixed WALLY-init-lib to return correctly even from traps from compressed instructions
2023-04-07 20:24:33 -07:00
David Harris
a49f1f785e
Fixed enabling machine timer interrupt
2023-04-06 22:18:33 -07:00
David Harris
8ef9891e46
vm64 tests
2023-04-06 21:42:47 -07:00
David Harris
19c39628fa
Division cleanup
2023-04-06 21:42:34 -07:00
David Harris
6db65f30b1
Simplified integer division preprocessing in fdivsqrt
2023-04-06 16:43:28 -07:00
David Harris
4ce223281a
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-06 14:07:59 -07:00
David Harris
7ad05d9a42
Removed redundant stall signal to get spill coverage
2023-04-06 14:07:50 -07:00
Jacob Pease
b796b1b492
Build doesn't work. AXI Crossbar has problems.
2023-04-06 16:01:58 -05:00
Ross Thompson
a0471dd8bd
Merge branch 'main' of github.com:ross144/cvw
2023-04-06 15:33:24 -05:00
Ross Thompson
6cdfbef2ca
Added Jacob's ILA script.
2023-04-06 15:32:36 -05:00
Ross Thompson
07b946bc75
Fixed syntax error.
2023-04-06 15:10:55 -05:00
Ross Thompson
4407d3310c
Added note about strange vivado behavior not inferring block ram.
2023-04-06 15:09:35 -05:00
Ross Thompson
ee4cf5e94d
Similifed the no byte write enabled version of the sram model.
2023-04-06 14:18:41 -05:00
Kevin Thomas
a588a9eb5d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-06 12:38:41 -05:00
David Harris
17f96aa341
Update dvtestplan.md
2023-04-06 09:29:47 -07:00
David Harris
beade59349
Create dvtestplan.md
2023-04-06 09:23:09 -07:00
David Harris
1300d57d33
Merge pull request #214 from eroom1966/main
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Add in configuration for B extension
2023-04-06 09:08:20 -07:00
Lee Moore
83609218aa
Merge branch 'openhwgroup:main' into main
2023-04-06 16:31:49 +01:00
eroom1966
dc79710724
add support into configuration for Zb(a,b,c,s)
2023-04-06 16:30:14 +01:00
David Harris
1d39c4f823
Merge pull request #213 from eroom1966/main
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fix break to simulation testbench
2023-04-06 06:54:59 -07:00
eroom1966
47999784d6
fix break to simulation testbench
2023-04-06 14:45:41 +01:00
David Harris
4e3af7bca7
Merge pull request #211 from ross144/main
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Fixes the issue introduced by the fix for issue 203
2023-04-05 21:50:32 -07:00
Ross Thompson
e531b0103e
Fixed wally64/32priv test hangup.
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The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
2023-04-05 23:13:45 -05:00
Kevin Thomas
159c02e3f3
Merge branch 'main' of https://github.com/kjprime/cvw
2023-04-05 17:44:54 -05:00
Kevin Thomas
7c1ecfd97d
Merge branch 'openhwgroup:main' into main
2023-04-05 17:44:47 -05:00
Kevin Thomas
d7188d6d9c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-05 17:43:43 -05:00
Ross Thompson
7cdd12a40a
Merge pull request #206 from AlecVercruysse/coverage2
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i$ coverage improvements
2023-04-05 17:29:35 -05:00
David Harris
02053c5dc6
Merge pull request #210 from SydRiley/main
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Starting to extend fpu conditional coverage, reformatting ifu test cases.
2023-04-05 14:56:16 -07:00
Alec Vercruysse
ac3569d75c
Update ram1p1rwe (ce & we) coverage exlusion explanation
2023-04-05 14:54:58 -07:00
Sydeny
9e3d78de8b
Starting to extend fpu conditional coverage, reformating ifu test cases
2023-04-05 14:10:15 -07:00
Kevin Thomas
dab5074f29
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-05 15:33:10 -05:00
Kevin Thomas
4d30aff198
Formating white space
2023-04-05 15:30:55 -05:00
David Harris
32c5a1d83e
Merge pull request #205 from kbox13/my-single-change
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Increase LSU Coverage
2023-04-05 13:16:04 -07:00
Kevin Thomas
5ac49fa31f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-05 15:04:12 -05:00
David Harris
1257439cf8
Merge pull request #208 from ross144/main
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Fixes Issue 203
2023-04-05 13:03:30 -07:00
Ross Thompson
70aa5a5917
Merge pull request #207 from AlecVercruysse/cachesim
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Cache Simulator
2023-04-05 14:59:52 -05:00
Ross Thompson
da9cf02ba0
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-05 14:55:12 -05:00
Limnanthes Serafini
590f95d353
*.out removal
2023-04-05 12:50:26 -07:00
Limnanthes Serafini
baa537c5d3
*.out removal
2023-04-05 12:50:10 -07:00
Limnanthes Serafini
ecc580a140
*.out removal
2023-04-05 12:49:57 -07:00
Alec Vercruysse
570e86afc3
Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE
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To increase coverage. Read-only caches do not have flushes since
they do not have dirty bits.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
54df581ce6
make Cache Flush Logic dependent on !READ_ONLY_CACHE
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read-only caches do not have flush logic since they do not have to
deal with dirty bits.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
3419ef3651
remove ClearValid from cache
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The cachefsm hardwired ClearValid logic to zero.
This signal might've been added to potentially add extra functionality
later. Unless that functionality is added, however, it negatively
impacts coverage. If the goal is to maximize coverage, this signal
should be removed and only added when it becomes necessary.
2023-04-05 11:48:18 -07:00
