9 Commits

Author	SHA1	Message	Date
Ross Thompson	ec4a07de64	Movied tristate to test bench level.	2021-09-30 11:27:42 -05:00
Ross Thompson	db18aac9af	Partially sd card read on fpga.	2021-09-30 11:23:09 -05:00
Ross Thompson	99070127d8	Added debugging directives to system verilog.	2021-09-27 13:57:46 -05:00
Ross Thompson	f2c1ca4bd5	added support to due partial fpga simulation.	2021-09-26 15:00:00 -05:00
Ross Thompson	5bdd6a9d0c	Almost done writting driver for flash card reader.	2021-09-25 19:05:07 -05:00
Ross Thompson	3a15cc7872	We now have a rough sdc read routine.	2021-09-25 17:51:38 -05:00
Ross Thompson	232d4a554f	Have program which checks for sdc init and issues read, but read done is ... not correctly being read back by the software. The error is in how the sdc indicates busy.	2021-09-24 15:53:38 -05:00
Ross Thompson	0f87f68b9d	Added either the sdModel or constant driver for the SDC ports in all test benches.	2021-09-24 12:31:51 -05:00
Ross Thompson	144003cb41	FPGA test bench and test program.	2021-09-12 20:41:54 -05:00