Katherine Parry
9252d08b41
fpu imperas tests run
2021-05-01 02:18:01 +00:00
Thomas Fleming
e091f430e0
Clean up PMA checker and begin PMP checker
2021-04-29 02:20:39 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Ross Thompson
d7fea1ba3c
almost working icache.
2021-04-23 16:47:23 -05:00
Ross Thompson
c9bdaceddb
Fixed icache for 32 bit.
...
Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Thomas Fleming
e7822ce20c
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Thomas Fleming
4d4ca24640
Extend stall on leaf page lookups
2021-04-22 01:51:38 -04:00
Thomas Fleming
70c801331a
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Jarred Allen
757b64e487
Merge branch 'main' into cache
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Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
2021-04-14 18:24:32 -04:00
Thomas Fleming
ae888b5705
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/ebu/pagetablewalker.sv
2021-04-13 13:42:03 -04:00
Thomas Fleming
f0c926cf68
Move InstrPageFault to fetch stage
2021-04-13 13:39:22 -04:00
Teo Ene
0bffac2c74
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Jarred Allen
6ce4d44ae1
Merge from branch 'main'
2021-04-08 17:19:34 -04:00
Thomas Fleming
e807f5d771
Implement support for superpages
2021-04-08 02:44:59 -04:00
Ross Thompson
d901cfc848
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Thomas Fleming
5946b860ca
Comment out fpu from hart until module exists
2021-04-03 22:34:11 -04:00
Thomas Fleming
8f31e00f6a
Merge branch 'mmu' into main
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Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
2021-04-03 22:12:52 -04:00
Thomas Fleming
e04ad8f304
Fix extraneous page fault stall
2021-04-03 21:28:24 -04:00
Katherine Parry
08b31f7b2a
Integrated FPU
2021-04-03 20:52:26 +00:00
James E. Stine
9026357350
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
2021-04-02 06:27:37 -05:00
Thomas Fleming
f9bf2fbc01
Implement sfence.vma and fix tlb writing
2021-04-01 15:55:05 -04:00
Ross Thompson
f1107c5d7b
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
ushakya22
ba01d57767
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
Jarred Allen
fdecd6c56c
Clean up some stuff
2021-03-25 13:04:54 -04:00
Jarred Allen
e8e4e1bee2
rv64i linear control flow now working
2021-03-25 13:02:26 -04:00
Jarred Allen
2f5d854f87
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/src/uncore/dtim.sv
2021-03-25 12:10:26 -04:00
Thomas Fleming
89a2fe5741
Finish finite state machines for page table walker
2021-03-25 02:48:40 -04:00
Jarred Allen
1f01a12be9
Merge branch 'main' into cache
2021-03-23 23:35:36 -04:00
Shreya Sanghai
09b90557f7
PC counts branch instructions
2021-03-23 14:25:51 -04:00
Jarred Allen
50c961bbe4
Merge changes from main
2021-03-18 18:58:10 -04:00
Thomas Fleming
062c4d40da
Connect tlb, pagetablewalker, and memory
2021-03-18 14:35:46 -04:00
Jarred Allen
003242ae8a
Merge upstream changes
2021-03-14 14:57:53 -04:00
Thomas Fleming
e57b6cf18c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-03-11 00:15:58 -05:00
David Harris
fe4d288589
Initial untested implementation of AMO instructions
2021-03-11 00:11:31 -05:00
Jarred Allen
c0ee17b6ac
Merge upstream changes
2021-03-09 21:20:34 -05:00
Thomas Fleming
97e9baa316
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 13:35:44 -05:00
Thomas Fleming
e48dc38869
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
Jarred Allen
5da98b5381
Partial progress towards compressed instructions
2021-03-04 18:30:26 -05:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Thomas Fleming
8c410b6fbe
Install dtlb in dmem
2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5
Install tlb into ifu
2021-03-04 03:11:34 -05:00
David Harris
6f4e8b723e
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Ross Thompson
6191fcb1af
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
0258901865
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
38b8cc652c
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
Ross Thompson
c856003f73
RAS needs to be reset or preloaded. For now I just reset it.
...
Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
bbe0db3ebe
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
David Harris
adc5d5bc1a
Added MUL
2021-02-15 22:27:35 -05:00
David Harris
842c374de9
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
33110ed636
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
429f48e766
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
616830a3f0
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
David Harris
bb83fda1d8
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
David Harris
92bf1674b4
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
David Harris
1a3963bed0
Renamed DCU to DMEM
2021-02-01 18:52:22 -05:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
