Jordan Carlin
0312476fb3
Update tlb camline ASID coverage to use single file
2024-02-03 09:48:57 -08:00
Jordan Carlin
8633f263a2
Complete coverage of tlb camlines in IFU
2024-02-01 20:41:05 -08:00
David Harris
49714cb282
Fixed assertions to throw fatal error, improved nightly regression to have passing cases
2024-01-31 21:39:18 -08:00
David Harris
111f592613
factor divsqrt out of floating-point test cases to run on more derived configs
2024-01-31 14:52:15 -08:00
David Harris
171430a695
FPU and PMP tests
2024-01-21 14:41:22 -08:00
David Harris
74b242ce5c
Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow
2024-01-17 12:25:06 -08:00
David Harris
4cfc86140c
Zfa fmvh complete and passing tests:
2024-01-17 06:18:00 -08:00
David Harris
07e7e02241
Coded Zfa fmvp but no tests exist
2024-01-16 21:26:42 -08:00
David Harris
8654375f26
Zfa fminm/fmaxm/fltq/fleq implemented and tested
2024-01-16 20:03:54 -08:00
David Harris
1a77c08f6e
Fixed issues 575 and 477 about FPU tests failing when Zfh = 1.
2024-01-16 10:46:44 -08:00
David Harris
da4eca4854
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
2024-01-15 13:24:57 -08:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
David Harris
d229dc06ee
Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE
2024-01-02 00:35:17 -08:00
David Harris
52b6d1d163
restored tlbNAPOT coverage tests
2023-12-31 09:55:58 -08:00
David Harris
5dbca251d8
Defined new Zicboz and Zcb tests
2023-12-19 13:24:11 -08:00
David Harris
a138ef37b1
Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)
2023-12-15 19:26:50 -08:00
David Harris
38f4d9baf8
Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e
2023-12-15 05:05:53 -08:00
Rose Thompson
da59cb71a9
Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.
2023-11-13 14:12:27 -06:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
Rose Thompson
baacb6f6eb
Missed tests.vh.
2023-11-10 16:10:10 -06:00
naichewa
a08356fdaa
correct exclusion tags and reset testbench
2023-11-01 10:34:39 -07:00
naichewa
0ff9ce527d
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
naichewa
4941fe1769
sync fifo passes
2023-10-16 22:57:02 -07:00
David Harris
ac4216b43d
Incorporated new AMO tests from riscv-arch-test
2023-10-16 10:25:45 -07:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
91429f3f02
Initial TLB NAPOT tests
2023-08-29 12:39:24 -07:00
David Harris
8d3ff59673
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
Ross Thompson
cd3349bd26
Added rv32 cboz test.
2023-08-24 17:02:53 -05:00
David Harris
d801916d97
Merge pull request #383 from ross144/main
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Adds Zicbom support for D-cache only. I-cache not yet supported. Tests 32 and 64 bit versions. Please rebuild regressions wally32 and wally64. To save rebuild time edit lines 11-12 of tests/riscof/Makefile
2023-08-21 13:32:00 -07:00
Ross Thompson
310b700550
Have a working 32 bit cbom test!
2023-08-21 13:46:09 -05:00
Ross Thompson
d4c6ba627d
Working CBO tests for 64 bit!
2023-08-21 12:55:07 -05:00
David Harris
2738423441
Improved CSRU coverage with priv.S
2023-08-20 12:49:31 -07:00
David Harris
b04763bcf2
Commented SVADU requirements for wally32priv mmu tests
2023-07-04 11:34:07 -07:00
David Harris
5d6eb40c2d
Fixed embench to run all tests, even ones not in 1.0
2023-06-17 20:38:51 -07:00
David Harris
2db94e7ddd
Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete
2023-06-16 16:07:28 -07:00
Ross Thompson
664231c0da
Merge branch 'localhistory'
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Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
2023-05-22 10:13:31 -05:00
David Harris
7b0d1a7883
Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim
2023-05-16 11:37:01 -07:00
Ross Thompson
0904a9b97f
Swapped the m and k parameters for local history predictor.
2023-05-02 10:52:41 -05:00
Kevin Wan
9ca738547e
fixed tests.vh test lines
2023-04-28 07:47:59 -07:00
Kevin Wan
39c9cd5ee9
added tests for pmppriority module
2023-04-27 16:12:43 -07:00
Noah Limpert
4ec31de316
complete camline coverage on IFU and LSU
2023-04-27 14:26:10 -07:00
Noah Limpert
a0e71c26cb
Add in a test that makes match 3 = 0 for all tlb lines
2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126
Commiting changes to add coverage to ASID, Global, Megapage size checks.
2023-04-20 14:38:13 -07:00
David Harris
6e612a1693
Update tests.vh
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Missing comma from merge
2023-04-19 06:23:05 -07:00
David Harris
4cbffd7972
Merge branch 'main' into coverage4
2023-04-19 06:16:07 -07:00
David Harris
b63dff098a
Merge branch 'main' into main
2023-04-19 04:50:12 -07:00
David Harris
156a098884
Merge branch 'main' into main
2023-04-19 04:46:51 -07:00
Alec Vercruysse
b3a3af8ed3
add D$ test case to trigger a FlushStage while SetDirtyWay=1
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This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44
Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
Liam
9b72d6ac37
Update tests.vh
2023-04-18 23:15:47 -07:00
