Thomas Fleming
394051c02f
Begin hardware page table walker
2021-03-03 17:13:45 -05:00
Thomas Fleming
d8ac9034b7
Create virtual memory ad-hoc test
...
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
2021-03-03 17:06:37 -05:00
Teo Ene
4562c61af3
Fix to last push
2021-03-03 15:20:38 -06:00
Teo Ene
37bf3d836f
Updated coremark .do file for easier debugging
2021-03-03 15:10:39 -06:00
Teo Ene
e6044b9867
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-02 17:23:44 -06:00
Teo Ene
e7f7f980b3
Updated coremark .do file for easier debugging
2021-03-02 17:23:39 -06:00
Noah Boorstin
21b1c4163c
busybear: add sim-busybear and sim-busybear-batch based on sim-wally
2021-03-01 21:01:15 +00:00
Noah Boorstin
62b441f3f5
busybear: probably discovered bug in ahb code
2021-03-01 20:56:04 +00:00
Noah Boorstin
965d48afe7
busybear: only check pc when it actually changes
2021-03-01 19:08:35 +00:00
Noah Boorstin
4833b36535
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
Noah Boorstin
26d4024b33
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
David Harris
9bcddfa5dd
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-01 00:09:55 -05:00
David Harris
2543c29839
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Teo Ene
babe6ce9db
Properly implemented the fix from commit 31c07b2adc
2021-02-28 22:22:04 -06:00
Noah Boorstin
e4bda37354
Merge branch 'main' into busybear
2021-02-28 20:48:23 +00:00
Noah Boorstin
1858c32e9d
add .nfs* files to gitignore
2021-02-28 20:48:01 +00:00
Noah Boorstin
bcc0010498
Merge branch 'main' into busybear
2021-02-28 20:45:08 +00:00
Noah Boorstin
f306d2d2e1
busybear: start preloading bootmem
2021-02-28 20:43:57 +00:00
Noah Boorstin
db86d20d11
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Noah Boorstin
a03796a519
busybear: change sstatus, mstatus reset value
2021-02-28 16:19:03 +00:00
Noah Boorstin
6e70ae8b3d
busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
Noah Boorstin
edd5e9106d
busybear: remove gpio, start adding 2nd ram
2021-02-28 06:02:40 +00:00
Noah Boorstin
e5e345d161
busybear: instantiate normal wallypipelinedsoc
2021-02-28 06:02:21 +00:00
Ross Thompson
7592a0dacb
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
37e6a45d76
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
David Harris
cf03afa880
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
015b632eb1
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
kaveh pezeshki
c7863d58cd
merged with main to integrate with AHB
2021-02-26 05:37:10 -08:00
Noah Boorstin
ab9247d625
busybear: add main ram loading, better instr checking also
2021-02-26 20:26:54 +00:00
kaveh Pezeshki
ad631ec3a1
fixed sensitivity list on error checking always block, removed useless once and for all
2021-02-26 13:41:16 -05:00
kaveh pezeshki
d32421822c
restored
2021-02-26 02:22:08 -08:00
David Harris
b16846bddb
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
24f767a404
Retimed peripherals for AHB interface
2021-02-26 00:55:41 -05:00
Brett Mathis
4e6caf64d9
Fcmp/Fsgn pipeline modules
2021-02-25 18:22:30 -06:00
David Harris
c060e427f0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-25 15:49:38 -05:00
David Harris
a16fd95eed
Restored to working multiplier after Lab 2
2021-02-25 15:32:43 -05:00
Brett Mathis
ec82453ba1
FPU Assembly tests
2021-02-25 14:32:36 -06:00
Teo Ene
6be5bb1f84
Fixed previous commit
2021-02-25 11:24:44 -06:00
Teo Ene
31c07b2adc
Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.
2021-02-25 11:23:01 -06:00
Teo Ene
61b872a3e8
Changed TIMBASE in coremark config file
2021-02-25 11:03:41 -06:00
Teo Ene
544df9e18c
Merge remote-tracking branch 'origin/lab3' into main
2021-02-25 10:28:20 -06:00
Teo Ene
c47872c2af
Changed .do file back to run all
2021-02-25 09:58:54 -06:00
David Harris
d00d42cf9a
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
3b6807368f
removed WALLY ALU tests to avoid merge conflict with main branch
2021-02-25 00:15:22 -05:00
Teo Ene
3e5de35fc4
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
kaveh pezeshki
3bb8e0d918
condensed always blocks to avoid race conditions
2021-02-24 11:35:28 -08:00
Noah Boorstin
3d82ceffb7
busybear: preload bootram
...
thanks to Prof Stine for the .do file commands
@kaveh can you check line 201? it does nothing, but things break when
I remove that line
2021-02-24 18:46:09 +00:00
David Harris
f5e9c91193
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
kaveh pezeshki
b36a5614b4
added comments for RAM and bootram, removed trailing whitepace
2021-02-23 21:28:33 -08:00
Noah Boorstin
c8e9edcc43
busybear: add bootram section in the same manner as ram
2021-02-24 02:02:28 +00:00
