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Configurable RISC-V Processor
186 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
31c07b2adc
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Teo Ene 31c07b2adc Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.
2021-02-25 11:23:01 -06:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now. 2021-02-25 11:23:01 -06:00
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.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor