Liam
7bf2ee5418
pmpaddr0 and pmpaddr2 test cases
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Writing 0x00170000 and 0x17000000 to pmpaddr0 and pmpaddr2.
Increased IFU coverage from 83.53% to 83.68% and LSU coverage from 93.29% to 93.45%.
2023-04-25 15:37:04 -07:00
David Harris
086556310c
Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
2023-04-22 12:22:45 -07:00
Liam
c2f441724b
pmpcfg test cases
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Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
2023-04-21 20:43:37 -07:00
Noah Limpert
a0e71c26cb
Add in a test that makes match 3 = 0 for all tlb lines
2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126
Commiting changes to add coverage to ASID, Global, Megapage size checks.
2023-04-20 14:38:13 -07:00
Liam
4f57dca0dc
Add pmpcfg test cases increasing IFU coverage
2023-04-19 11:58:22 -07:00
David Harris
4cbffd7972
Merge branch 'main' into coverage4
2023-04-19 06:16:07 -07:00
David Harris
b63dff098a
Merge branch 'main' into main
2023-04-19 04:50:12 -07:00
Alec Vercruysse
b3a3af8ed3
add D$ test case to trigger a FlushStage while SetDirtyWay=1
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This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44
Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
Liam
d74768ce04
Add test cases for pmpcfg.S
2023-04-18 23:06:52 -07:00
Kevin Wan
b5a3ff2d2d
a
2023-04-18 22:09:50 -07:00
Kevin Wan
c91784bd5a
Merge branch 'main' of https://github.com/koooo142857/cvw into main
2023-04-18 21:55:06 -07:00
koooo142857
c9018b8204
Merge branch 'openhwgroup:main' into main
2023-04-18 21:53:46 -07:00
Kevin Wan
771124e265
Completely covers all PMPCFG_ARRAY_REGW cases
2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d
PMPCFG_ARRAY_REGW cases
2023-04-18 18:43:50 -07:00
Miles Cook
5e45fef838
Increase of TLB coverage in IFU
2023-04-17 18:35:03 -07:00
Diego Herrera Vicioso
16fd17be39
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
2023-04-15 23:13:39 -07:00
Dygore
cac9c2dc37
Added multiple tests to increase FPU coverage
2023-04-14 14:41:05 -05:00
Dylan
d7936a9214
Merge branch 'openhwgroup:main' into main
2023-04-14 00:36:57 -05:00
Dygore
69b4751162
Added tests for full coverage of the FPU result sign module
2023-04-14 00:36:12 -05:00
Noah Limpert
6a23bbea9d
add back K. Box and M. Cook Lsu test
2023-04-13 17:50:18 -07:00
Noah Limpert
3683139637
make pull request more clean
2023-04-13 17:44:09 -07:00
Noah Limpert
b35d5bdbdb
Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways"
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This reverts commit 6acf1dadda
2023-04-13 17:40:39 -07:00
Noah Limpert
d012715a60
Revert "Test File for Pull Request, Attempt to fill all four ways"
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This reverts commit e887341c80
2023-04-13 17:28:37 -07:00
Noah Limpert
034dabee54
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-13 17:00:48 -07:00
Noah Limpert
a0a9d35d19
update tests.vh, add tlbKP to load all lines of tlb
2023-04-13 15:13:55 -07:00
Dygore
4854e09124
Added a test for denormalized FP numbers
2023-04-13 16:39:27 -05:00
Noah Limpert
276ce87582
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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pull in changes to trap handler so that permissions should change correctly
2023-04-13 12:34:27 -07:00
Alexa Wright
23d0d45bf6
Fixed exception handling to handle ecalls properly
2023-04-13 09:23:32 -07:00
Kip Macsai-Goren
34200e8c76
restored original virt mem tests when svadu is not supported
2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
c4766c8a02
renamed virt mem tests to include svadu
2023-04-11 18:46:37 -07:00
Kip Macsai-Goren
b2d6084eea
removed unnecessary 'deadbeef's at the end of reference outputs
2023-04-11 18:32:04 -07:00
Kip Macsai-Goren
a82c0a7780
Modified virt mem tests to do correct r/w when svadu is enabled
2023-04-11 18:08:30 -07:00
Kip Macsai-Goren
e0b938b409
Removed Trap outputs from writes covered by SVADU
2023-04-11 17:41:57 -07:00
Kip Macsai-Goren
a899606c2b
Removed Sail from virt mem tests due to sail not recognizing SVADU
2023-04-11 17:41:31 -07:00
Kip Macsai-Goren
19305fe60a
Added sail simulation to priv tests that support it
2023-04-11 13:26:59 -07:00
Noah Limpert
748c8dc234
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-10 19:01:32 -07:00
David Harris
90c9f29beb
Merge pull request #226 from SydRiley/main
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Increased coverage for the fpu by adding directed tests to toggle signals
2023-04-09 21:52:11 -07:00
Kevin Box
59e7c9371a
Create new pmp tests
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configures all pmpcfg registers in each different address range.
2023-04-09 16:29:57 -07:00
Noah Limpert
41c79303c6
3rd attempt to resolve conflict in lsu.S file
2023-04-09 15:52:18 -07:00
Sydeny
f4caa62efc
Increasing coverage for the fpu by adding directed tests to toggle signals
2023-04-09 13:33:12 -07:00
Diego Herrera Vicioso
5f9c443781
Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs.
2023-04-08 16:40:36 -07:00
David Harris
b27199e276
Added vm64check tests to cover IMMU vm64
2023-04-07 21:14:52 -07:00
David Harris
0d2de13990
Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf
2023-04-07 21:11:01 -07:00
David Harris
bf9db11a57
Fixed priv.S to initialize stimecmp and agree with ImperasDV
2023-04-07 20:44:01 -07:00
David Harris
16eca598ba
Fixed WALLY-init-lib to return correctly even from traps from compressed instructions
2023-04-07 20:24:33 -07:00
David Harris
a49f1f785e
Fixed enabling machine timer interrupt
2023-04-06 22:18:33 -07:00
David Harris
8ef9891e46
vm64 tests
2023-04-06 21:42:47 -07:00
David Harris
02053c5dc6
Merge pull request #210 from SydRiley/main
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Starting to extend fpu conditional coverage, reformatting ifu test cases.
2023-04-05 14:56:16 -07:00
