11 Commits

Author	SHA1	Message	Date
David Harris	3cb5cd0cb1	simulator cleanup	2024-04-20 14:12:55 -07:00
David Harris	c8e7a6990d	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-04-20 11:44:27 -07:00
David Harris	bf2f6859e4	Changed Verilog makefile to print transcript to stdout by default like Questa; redirected to logfile elsewhere	2024-04-20 11:27:54 -07:00
Kunlin Han	91a88fa46c	Update sim/verilator/Makefile with more comments and merging variables.	2024-04-17 09:52:54 -07:00
Kunlin Han	392eedb342	Update sim/verilator/Makefile with constants for simplicity.	2024-04-16 18:54:11 -07:00
Kunlin Han	6f6b1fd1fd	Add extra path to search for deriv/buildroot.	2024-04-16 18:45:21 -07:00
Kunlin Han	7b5972ea82	Merge branch 'verilator_getenv' into wsim_verilator	2024-04-12 15:27:09 -07:00
Kunlin Han	4d9de94029	Add support for getenvval as wrapper for Verilator's getenv.	2024-04-12 14:59:04 -07:00
Kunlin Han	a55bb01d1d	Update README and put logs in the right places.	2024-04-11 20:16:55 -07:00
Kunlin Han	e25177cf4c	Add verilator support for wsim.	2024-04-11 20:02:20 -07:00
David Harris	a8a03d6011	Reorganizing sim directory for multiple simulators	2024-04-05 18:19:46 -07:00