Kip Macsai-Goren
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709f8e6e0d
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fixed double multiplication on vectored interrupts
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2022-03-28 19:12:31 +00:00 |
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Kip Macsai-Goren
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eb337fd3e1
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added test config that doesn't use compressed instructions for privileged tests
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2022-03-28 19:12:31 +00:00 |
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Ross Thompson
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09ff5c2c45
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Updated debug2.xdc ila constraints to match rtl.
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2022-03-28 10:52:26 -05:00 |
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Ross Thompson
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668eb828d6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-28 10:23:25 -05:00 |
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Ross Thompson
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5f88536730
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Temporary change of plic uart id to 10.
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2022-03-28 10:23:20 -05:00 |
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bbracker
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501dc7cd68
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fix genCheckpoint.sh binary memory dump
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2022-03-27 20:54:59 -07:00 |
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bbracker
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9b5bbd29b4
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change genCheckpoint.sh to only log 128MB of RAM
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2022-03-27 19:16:39 -07:00 |
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bbracker
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4e1b50e50c
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fix parseGDBtoTrace.py to expect the CSRs that QEMU actually prints out
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2022-03-27 19:05:44 -07:00 |
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bbracker
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800bc85519
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refactored buildroot configuration
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2022-03-27 15:13:03 -07:00 |
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bbracker
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0eeb6cc5b5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-27 15:11:42 -07:00 |
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bbracker
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8d5c231a13
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change devicetree to expect only 128MB of RAM
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2022-03-27 15:11:36 -07:00 |
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Skylar Litz
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f91fb7a388
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add AtemptedInstructionCount signal
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2022-03-26 21:28:57 +00:00 |
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Skylar Litz
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62a330c290
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update to match new filesystem organization
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2022-03-26 21:28:32 +00:00 |
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Kip Macsai-Goren
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7ae1d14191
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added basic trap tests that do not pass regression yet. updated signature adresses
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2022-03-25 22:57:41 +00:00 |
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Ross Thompson
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61c714ebe6
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I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.
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2022-03-25 13:10:31 -05:00 |
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Ross Thompson
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4ba0d1d662
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-25 11:01:01 -05:00 |
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Ross Thompson
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fe896bff8e
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Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
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2022-03-24 23:47:28 -05:00 |
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bbracker
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6f6663cd67
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fix multiple-context PLIC checkpoint generation
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2022-03-25 01:02:22 +00:00 |
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bbracker
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d33de3ef6b
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tabs vs spaces disagreement
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2022-03-24 17:11:41 -07:00 |
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bbracker
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4b376e2834
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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71aad2d213
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Moved WriteDataM register into LSU.
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2022-03-23 14:17:59 -05:00 |
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Ross Thompson
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8f74fd2a50
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-23 14:10:38 -05:00 |
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Katherine Parry
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7cf994526a
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fixed typo in unpack.sv
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2022-03-23 18:26:59 +00:00 |
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Ross Thompson
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af435ab591
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Another change required for forcing to work correctly with MIE/MIP and SIE/SIP.
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2022-03-23 10:26:17 -05:00 |
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Ross Thompson
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aa60b57fb3
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Cleanup in testbench-linux.sv.
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2022-03-22 22:34:38 -05:00 |
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Ross Thompson
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33b9b5423d
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reverted temporary change to configs.
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2022-03-22 22:31:34 -05:00 |
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Katherine Parry
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fcd23a006e
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fixed lint error in fpudivsqrtrecur.sv
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2022-03-23 03:24:41 +00:00 |
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Ross Thompson
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849707f161
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Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.
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2022-03-22 22:04:06 -05:00 |
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Ross Thompson
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c233ef9768
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Reverted change to configuration which caused issue with lint.
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2022-03-22 21:44:08 -05:00 |
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Ross Thompson
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b2487f4b72
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-22 21:28:50 -05:00 |
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Ross Thompson
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4ca9458534
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added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
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2022-03-22 21:28:34 -05:00 |
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Katherine Parry
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23adb2dd03
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unpack.sv cleanup
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2022-03-23 01:53:37 +00:00 |
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Ross Thompson
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e6b42cb10f
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Added spoof of uart addresses +0x2 and +0x6.
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2022-03-22 16:52:27 -05:00 |
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Ross Thompson
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ca8fb45367
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Added comment about needed fix to misaligned fault.
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2022-03-22 16:52:07 -05:00 |
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Katherine Parry
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e3d01c875b
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FMA parameterized and FMA testbench reworked
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2022-03-19 19:39:03 +00:00 |
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Ross Thompson
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ee4b38dce3
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dtim writes are supressed on non cacheable operation.
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2022-03-12 00:46:11 -06:00 |
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Ross Thompson
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86cc758354
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cleanup of ram.sv
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2022-03-11 18:09:22 -06:00 |
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Ross Thompson
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d43e868e5f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-11 15:42:10 -06:00 |
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Ross Thompson
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7a25d577ba
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Added new asserts to testbench.
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2022-03-11 15:41:53 -06:00 |
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Ross Thompson
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67ff8f27f4
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Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
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2022-03-11 15:18:56 -06:00 |
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Ross Thompson
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9dce2a0679
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Towards allowing dtim + bus.
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2022-03-11 14:58:21 -06:00 |
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Kip Macsai-Goren
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9d0a9f0747
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added preliminary files for trap/priv tests. These DO NOT pass make yet because if interrrupt handling problems
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2022-03-11 20:00:54 +00:00 |
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Kip Macsai-Goren
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026354f09f
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removed compressed instructions from gcc make for privilege tests
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2022-03-11 19:09:40 +00:00 |
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Kip Macsai-Goren
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88897da30b
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Added interrupt support (not exiting correctly yet), macros for causing traps.
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2022-03-11 19:09:16 +00:00 |
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Ross Thompson
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6e24a807f6
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mild cleanup.
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2022-03-11 13:05:47 -06:00 |
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Ross Thompson
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b7a680ec2a
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Moved subcachelineread inside the cache. There is some ugliness to still resolve.
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2022-03-11 12:44:04 -06:00 |
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Ross Thompson
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a18f06c20b
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Moved subcacheline read inside the cache.
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2022-03-11 11:03:36 -06:00 |
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Ross Thompson
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52cc852600
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removed unused parameter.
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2022-03-11 10:43:54 -06:00 |
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Ross Thompson
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7f0c5cc847
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atomic cleanup.
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2022-03-10 18:56:37 -06:00 |
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Ross Thompson
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257015a2df
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Name changes.
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2022-03-10 18:50:03 -06:00 |
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